Integrating logic retiming and register placement

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Integrating logic retiming and register placement

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 136 - 139

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Tzu-Chieh Tien	Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 300, R.O.C.
Hsiao-Pin Su	Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 300, R.O.C.
Yu-Wen Tsay	Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 300, R.O.C.
Yih-Chih Chou	Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 300, R.O.C.
Youn-Long Lin	Department of Computer Science, Tsing Hua University, Hsin-Chu, Taiwan 300, R.O.C.

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 6, Citation Count: 7

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	T. Soyata, E. Friedman, and 3. H. Mulligan, Jr., "Incorporating Interconnect, Register, and Clock Distribution Delays into the Retlming Process," IEEE Trans. on Computer-Aided Desi#n, vol.16, pp.105-120, Jan. 1997.
	3	K. N. Lalgudi and M. C. Papaefthymiou, "Retlming Edge- Triggered Circuits Under General Delay Models," IEEE 2~ans. on Computer-Aided Design, voi.16, pp.1393-1408, Dec. 1997.
	4	Narendra Shenoy , Richard Rudell, Efficient implementation of retiming, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.226-233, November 06-10, 1994, San Jose, California, United States
	5	W.-J. Chen, W.-K. Cheng, T.-F. Lee, C.-H. Wu, and Y.-L. Lin, "On the Relationship between Sequential Logic Retiming and Loop Folding," in Proc. of Synthesis and Simulation Mee~.ng and International Interchange, SASII%fI'93, Japan, pp.384-393, Oct. 1993.
	6	C. V. Schimpfle, Sven Simon, and Josef A Nossek, "Optimal placement of registers in data paths for low power design," in Proc. of the 1997 IEEE Int. Syrup. on Circuits and Systems, ISGAS'97, vol.3, pp.2160-2163, June 1997.
	7	A. EI-Maleh, T. E. Marchok, I. Rajski, and W. Maly, "Behavior and Testability Preservation Under the Retiming Transformation," IEEE Trans. on Gomput,r-Aided Design, vol. 16, pp.528- 542, May 1997.
	8	Narendra V. Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Retiming of Circuits with Single Phase Transparent Latches, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.86-89, October 14-16, 1991
	9	H. I. Touati, and R. K. Brayton,"Computing the Initial States of Retlmed Circuits," IEEE Trans. on Oomputer-Aided Design, voi.12, pp.157-162, Jan. 1993.
	10	C.-S. Choy, T.-S. Cheung, and K.-K. Wong, "Incremental Layout Placement Modification Algorithms," IEEE Trans. on Computer-Aided Design, vol.15, pp.437-445, Apr. 1996.
	11	Massoud Pedram , Narasimha Bhat, Layout driven technology mapping, Proceedings of the 28th conference on ACM/IEEE design automation, p.99-105, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127635]
	12	W. C. Elmore, "The transient response of dampen linear networks with particular regard to wide band amplifiers," J. Appl. Phys., vol.19, pp.55-63, 1948.
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	14	TCB650 Library, 0.5urn Standard Cell Data Book, TSMC, Apr. 1996.

CITED BY 7

	A. Ranjan , A. Srivastava , V. Karnam , M. Sarrafzadeh, Layout aware retiming, Proceedings of the 11th Great Lakes symposium on VLSI, p.25-30, March 2001, West Lafayette, Indiana, United States
	Ingmar Neumann , Wolfgang Kunz, Placement driven retiming with a coupled edge timing model, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Jason Cong , Xin Yuan, Multilevel global placement with retiming, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Mongkol Ekpanyapong , Sung Kyu Lim, Performance-driven global placement via adaptive network characterization, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.137-142, January 27-30, 2004, Yokohama, Japan
	Dennis K. Y. Tong , Evangeline F. Y. Young, Performance-driven register insertion in placement, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Yu Hu , Yan Lin , Lei He , Tim Tuan, Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.2, p.1-29, April 2008
	Chris Chu , Evangeline F. Y. Young , Dennis K. Y. Tong , Sampath Dechu, Retiming with Interconnect and Gate Delay, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.221, November 09-13, 2003