Optimal 2-D cell layout with integrated transistor folding

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Optimal 2-D cell layout with integrated transistor folding

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 128 - 135

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Avaneendra Gupta	Cadence Design Systems, Inc., 555 River Oaks ParMay, 1A1, San Jose, CA
John P. Hayes	Dept. of EECS, University of Michigan, 1301 Beal Avenue, Ann Arbor, MI

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 6, Downloads (12 Months): 44, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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