Finding all simple disjunctive decompositions using irredundant sum-of-products forms

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Finding all simple disjunctive decompositions using irredundant sum-of-products forms

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 111 - 117

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Shin-ichi Minato	NTT Optical Network Systems Labs., Kanagawa, Japan
Giovanni De Micheli	Stanford University, Stanford, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 8, Citation Count: 7

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. Ashenhurst. ~'The Decomposition of Switching Functions." In Proc. an International Symposium on the Theory of Swilchinq. pp. 74-116. Apr. 1957.
	2	Robert King Brayton , Alberto L. Sangiovanni-Vincentelli , Curtis T. McMullen , Gary D. Hachtel, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Norwell, MA, 1984
	3	R'. Bravton, R. Rudell, A. S.-Vincentelli. and A. Wang, "MIS: "3, klultiple-Level Logic Optimization System," IEEE Trans. on CAD. (;(6), pp. 1062-1081, Nov. 1987.
	4	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	5	Valeria Bertacco , Maurizio Damiani, The disjunctive decomposition of logic functions, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.78-82, November 09-13, 1997, San Jose, California, United States
	6	Yung-Te Lai , Massoud Pedram , Sarma B. K. Vrudhula, BDD based decomposition of logic functions with application to FPGA synthesis, Proceedings of the 30th international conference on Design automation, p.642-647, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165078]
	7	S. Minato, "Fast Generation of Irredundant Sum-of- Products Forms from Binary Decision Diagrams," In Proc. Synthesis and simulation Meeting and International Interchange (SASI;}H'92), pp. 64-73, Apr. 1992.
	8	S. Minato, "Fast Factorization Method for Implicit Cube Set Representation", IEEE Trans. on CAD, 15(4), pp.377-384. A~. 199.6.
	9	E. Morreale, "'Kecurslve Operators for Prime Implicant and Irredundant Normal Form Determination," IEEE Trans. Compul.. C-19(6), pp. 504-509, June 1970.
	10	3. Roth and R. Karp, "Minimization Over Boolean Graphs," IBM Journal pj~. 22%2.38. Anr. 1962.
	11	T. S*asao, :FPGA Design 5y Generalized Functional Decomposition," In T. Sasao, editor, Logic Synthesis and Optimization, pp. 233-258, Kluwer Academic Publishers, 1993.
	12	Hiroshi Sawada , Shigeru Yamashita , Akira Nagoya, Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables, Proceedings of the 7th Great Lakes Symposium on VLSI, p.39, March 13-15, 1997

CITED BY 7

	Tsutomu Sasao , Ken-ichi Kurimoto, Three parameters to find functional decompositions, Proceedings of the 2000 conference on Asia South Pacific design automation, p.259-264, January 2000, Yokohama, Japan
	Alan Mishchenko , Bernd Steinbach , Marek Perkowski, An algorithm for bi-decomposition of logic functions, Proceedings of the 38th conference on Design automation, p.103-108, June 2001, Las Vegas, Nevada, United States
	Masahiro Fujita , Yusuke Matsunaga , Maciej Ciesielski, Multi-level logic optimization, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Andrés Martinelli , René Krenz , Elena Dubrova, Disjoint-support Boolean decomposition combining functional and structural methods, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.597-599, January 27-30, 2004, Yokohama, Japan
	Lech Jóźwiak , Aleksander S´lusarczyk, General decomposition of incompletely specified sequential machines with multi-state behavior realization, Journal of Systems Architecture: the EUROMICRO Journal, v.50 n.8, p.445-492, August 2004
	Tomas Bengtsson , Andrés Martinelli , Elena Dubrova, A BDD-based fast heuristic algorithm for disjoint decomposition, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	L. Jóźwiak , S. Biegański , A. Chojnacki, Information-driven circuit synthesis with the pre-characterized gate libraries, Journal of Systems Architecture: the EUROMICRO Journal, v.51 n.6-7, p.405-423, June-July 2005