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Synthesis of BIST hardware for performance testing of MCM interconnections
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Source International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California, United States
Pages: 69 - 73  
Year of Publication: 1998
ISBN:1-58113-008-2
Authors
Rajesh Pendurkar  School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA
Abhijit Chatterjee  School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA
Yervant Zorian  LogicVision, Inc., 101 Metro Drive, San Jose, CA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 1,   Downloads (12 Months): 7,   Citation Count: 1
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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H. Chang and J. Abraham, "Delay Test Techniques for Boundary Scan Based Architectures" Proc. of International Test Conference, pp 263-273, 1986.
 
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C. Chang and C. Su, "An Universal BIST Methodology for Interconnects,' Proc. of International Test Conference, pp 1615-1618, 1993.
 
4
Chih-Ang Chen and S. K. Gupta, "BIST/DFT for Performance Testing of Bare Dies and MCMs" Proc. of Electro '94, pp 803-812, 1994.
 
5
Chih-Ang Chert and S. K. Gupta, "Design of Efficient BIST Test Pattern Generators for Delay Testing,' Proc. of IEEE Transactions on CAD of Integrated Circuits and Systems, Vot 15, No. 12, pp 1568-75, 1996.
 
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A. Hassan, V. Agarwal, B. Nadeau-Dostie and J. Rajski, "BIST of PCB Interconnects Using Boundary-Scan Architecture;' IEEE Trans. on Computer Aided Design, Vol. I 1, No. 10, pp. 1278-1287, 1992.
 
8
D. Isaacson and R. Madsen, Markov Chains Theory and Applications, John Wiley &Sons, 1976.
 
9
J. Koeter and S. Sparks, "Interconnect Testing Using BIST Embedded in IEEE 1149.1 Designs,' Proe. of International ASIC Conference & Exhibition, pp P11-2.I-P11-2.4, 1991.
 
10
S. Pilarski and A. Pierzynska, "BIST and Delay Fault Detection" Proe. of CICC, pp 13.2.1-13.2.4, 1992.
 
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C. Su, "Random Testing of Interconnects in a Boundary Scan Environment,' Proc. of international Test Conference, pp 372-38 I, 1992.
 
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L.T. Wang and E. J. McCluskey, "Hybrid Designs Generating Maximum-Length Sequences,' IEEE Trans. on Computer Aided Design, Vol. 7, No.l, pp. 91-99, 1988.
 
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T.W. Williams, W. Daehn, M. Gruetzner and C. W. Stark, "Bounds and Analysis of Aliasing Errors in Linear Feedback Shift Registers," Proc. of IEEE Trans. Computer Aided Design, Vol. 7, pp 75-83, 1988.
 
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Collaborative Colleagues:
Rajesh Pendurkar: colleagues
Abhijit Chatterjee: colleagues
Yervant Zorian: colleagues