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CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 62 - 67

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Robert P. Dick	Department of Electrical Engineering, Princeton University, 2 Princeton, New Jersey
Niraj K. Jha	Department of Electrical Engineering, Princeton University, 2 Princeton, New Jersey

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 27, Citation Count: 23

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	8	Wayne H. Wolf, An architectural co-synthesis algorithm for distributed, embedded computing systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.2, p.218-229, June 1997 [doi>10.1109/92.585225]
	9	Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
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	13	David E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1989
	14	Robert P. Dick , Niraj K. Jha, MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.522-529, November 09-13, 1997, San Jose, California, United States
	15	Robert P. Dick , David L. Rhodes , Wayne Wolf, TGFF: task graphs for free, Proceedings of the 6th international workshop on Hardware/software codesign, p.97-101, March 15-18, 1998, Seattle, Washington, United States
	16	"Computer design." Product trends sections ofvol. 35: n. 2, 6, 8, 9, vol. 36: n. 1, 9, and vol. 37: n. 1-3.

CITED BY 23

	U. Nagaraj Shenoy , Prith Banerjee , Alok Choudhary, A system-level synthesis algorithm with guaranteed solution quality, Proceedings of the conference on Design, automation and test in Europe, p.417-425, March 27-30, 2000, Paris, France
	Yanbing Li , Tim Callahan , Ervan Darnell , Randolph Harr , Uday Kurkure , Jon Stockwood, Hardware-software co-design of embedded reconfigurable architectures, Proceedings of the 37th conference on Design automation, p.507-512, June 05-09, 2000, Los Angeles, California, United States
	Byungil Jeong , Sungjoo Yoo , Sunghyun Lee , Kiyoung Choi, Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs, Proceedings of the 2000 conference on Asia South Pacific design automation, p.169-174, January 2000, Yokohama, Japan
	Daler N. Rakhmatov , Sarma B. K. Vrudhula, Hardware-software bipartitioning for dynamically reconfigurable systems, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
	Juanjo Noguera , Rosa M. Badia, Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
	Sunghyun Lee , Sungjoo Yoo , Kiyoung Choi, Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
	Juanjo Noguera , Rosa M. Badia, HW/SW codesign techniques for dynamically reconfigurable architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.4, p.399-415, August 2002
	Juanjo Noguera , Rosa M. Badia, System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures, Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, October 30-November 01, 2003, San Jose, California, USA
	An algorithm for synthesis of large time-constrained heterogeneous adaptive systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.2, p.207-225, April 2001
	J. Noguera , R. Badia, A HW/SW partitioning algorithm for dynamically reconfigurable architectures, Proceedings of the conference on Design, automation and test in Europe, p.729, March 2001, Munich, Germany
	Ying Zhang , Robert Dick , Krishnendu Chakrabarty, Energy-aware deterministic fault tolerance in distributed real-time embedded systems, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Juanjo Noguera , Rosa M. Badia, Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling, ACM Transactions on Embedded Computing Systems (TECS), v.3 n.2, p.385-406, May 2004
	Gang Quan , James P. Davis , Siddhaveerasharan Devarkal , Duncan A. Buell, High-level synthesis for large bit-width multipliers on FPGAs: a case study, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
	Christian Haubelt , Stephan Otto , Cornelia Grabbe , Jürgen Teich, A system-level approach to hardware reconfigurable systems, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Mário P. Véstias , Horácio C. Neto, Co-synthesis of a configurable SoC platform based on a network on chip architecture, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Thilo Streichert , Christian Haubelt , Jürgen Teich, Online hardware/software partitioning in networked embedded systems, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Jiong Luo , Niraj K. Jha , Li-Shiuan Peh, Simultaneous dynamic voltage scaling of processors and communication links in real-time distributed embedded systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.4, p.427-437, April 2007
	Marco D. Santambrogio , Seda Ogrenci Memik , Vincenzo Rana , Umut A. Acar , Donatella Sciuto, A novel SoC design methodology combining adaptive software and reconfigurable hardware, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Robert P. Dick , Niraj K. Jha, MOCSYN: multiobjective core-based single-chip system synthesis, Proceedings of the conference on Design, automation and test in Europe, p.55-es, January 1999, Munich, Germany
	Le Yan , Jiong Luo , Niraj K. Jha, Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.30, November 09-13, 2003
	Li Shang , Niraj K. Jha, Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.345, January 07-11, 2002
	Sin Ming Loo , B. Earl Wells, Task Scheduling in a Finite-Resource, Reconfigurable Hardware/Software Codesign Environment, INFORMS Journal on Computing, v.18 n.2, p.151-172, Spring 2006
	Lech Jówiak , Sien-An Ong, Quality-driven model-based architecture synthesis for real-time embedded SoCs, Journal of Systems Architecture: the EUROMICRO Journal, v.54 n.3-4, p.349-368, March, 2008