Wireplanning in logic synthesis

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Wireplanning in logic synthesis

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 26 - 33

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Wilsin Gosti	Dept. of EECS, University of California, Berkeley, CA
Amit Narayan	Monterey Design Systems, Sunnyvale, CA
Robert K. Brayton	Dept. of EECS, University of California, Berkeley, CA
Alberto L. Sangiovanni-Vincentelli	Dept. of EECS, University of California, Berkeley, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 13, Citation Count: 17

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	6	Yuji Kukimoto , Robert K. Brayton, Hierarchical functional timing analysis, Proceedings of the 35th annual conference on Design automation, p.580-585, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277197]
	7	Ralph H. J. M. Otten , Robert K. Brayton, Planning for performance, Proceedings of the 35th annual conference on Design automation, p.122-127, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277071]
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CITED BY 17

	Prabhakar Kudva , Andrew Sullivan , William Dougherty, Metrics for structural logic synthesis, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.551-556, November 10-14, 2002, San Jose, California
	Luca P. Carloni , Kenneth L. McMillan , Alexander Saldanha , Alberto L. Sangiovanni-Vincentelli, A methodology for correct-by-construction latency insensitive design, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.309-315, November 07-11, 1999, San Jose, California, United States
	Hema Kapadia , Mark Horowitz, Using partitioning to help convergence in the standard-cell design automation methodology, Proceedings of the 36th ACM/IEEE conference on Design automation, p.592-597, June 21-25, 1999, New Orleans, Louisiana, United States
	Shih-Chieh Chang , Jung-Cheng Chuang , Zhong-Zhen Wu, Synthesis for multiple input wires replacement of a gate for wiring consideration, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.115-119, November 07-11, 1999, San Jose, California, United States
	Ron Ho , Ken Mai , Hema Kapadia , Mark Horowitz, Interconnect scaling implications for CAD, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.425-429, November 07-11, 1999, San Jose, California, United States
	Robert K. Brayton, The future of logic synthesis and verification, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Wilsin Gosti , Sunil P. Khatri , Alberto L. Sangiovanni-Vincentelli, Addressing the timing closure problem by integrating logic optimization and placement, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Shyam Ramji , Nagu R. Dhanwada, Design topology aware physical metrics for placement analysis, Proceedings of the 13th ACM Great Lakes symposium on VLSI, April 28-29, 2003, Washington, D. C., USA
	Giancarlo Beraudo , John Lillis, Timing optimization of FPGA placements by logic replication, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Chanseok Hwang , Massoud Pedram, Timing-driven placement based on monotone cell ordering constraints, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Miloš Hrkić , Miloš Hrkić , John Lillis , Giancarlo Beraudo, An approach to placement-coupled logic replication, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	A. I. Erzin , J. D. Cho, Concurrent Placement and Routing in the Design of Integrated Circuits, Automation and Remote Control, v.64 n.12, p.1988-1999, December 2003
	Hosung (Leo) Kim , John Lillis , Miloš Hrkić , Miloš Hrkić, Techniques for improved placement-coupled logic replication, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	S. Chatterjee , R. Brayton, A new incremental placement algorithm and its application to congestion-aware divisor extraction, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.541-548, November 07-11, 2004
	A. B. Kahng , S. Reda, Intrinsic shortest path length: a new, accurate a priori wirelength estimator, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.173-180, November 06-10, 2005, San Jose, CA
	Jurjen Westra , Dirk-Jan Jongeneel , Ralph H. J. M. Otten , Chandu Visweswariah, Time Budgeting in a Wireplanning Context, Proceedings of the conference on Design, Automation and Test in Europe, p.10436, March 03-07, 2003
	Stephen M. Plaza , Igor L. Markov , Valeria Bertacco, Optimizing non-monotonic interconnect using functional simulation and logic restructuring, Proceedings of the 2008 international symposium on Physical design, April 13-16, 2008, Portland, Oregon, USA