Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers

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Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers

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International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents

Barcelona, Spain

Pages: 388 - 397

Year of Publication: 1998

ISBN:1-58113-058-9

Author

Norman P. Jouppi

Digital Equipment Corporation Western Research Lab, 100 Hamilton Ave., Palo Alto, CA

Sponsors

IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 54, Downloads (12 Months): 108, Citation Count: 9

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	J.-L. Baer , W.-H. Wang, On the inclusion properties for multi-level cache hierarchies, Proceedings of the 15th Annual International Symposium on Computer architecture, p.73-80, May 30-June 02, 1988, Honolulu, Hawaii, United States
	2	Borg, Anita, Kessler, Rick E., Lazana, Georgia, and Wall, David W. Long Address Traces from RISC Machines: Generation and Analysis. Tech. Rept. 89/14, Digital Equipment Corporation Western Research Laboratory, September, 1989.
	3	Digital Equipment Corporation, Inc. VAX Hardware Handbook, volume 1 - 1984. Maynard, Massachusetts, 1984.
	4	Joel S. Emer , Douglas W. Clark, A Characterization of Processor Performance in the vax-11/780, Proceedings of the 11th annual international symposium on Computer architecture, p.301-310, January 1984
	5	Eustace, Alan. Private communication.
	6	M. K. Farrens , a. R. Pleszkun, Improving performance of small on-chip instruction caches, Proceedings of the 16th annual international symposium on Computer architecture, p.234-241, April 1989, Jerusalem, Israel
	7	Mark Donald Hill , Alan Jay Smith, Aspects of cache memory and instruction buffer performance, 1987
	8	N. P. Jouppi , D. W. Wall, Available instruction-level parallelism for superscalar and superpipelined machines, Proceedings of the third international conference on Architectural support for programming languages and operating systems, p.272-282, April 03-06, 1989, Boston, Massachusetts, United States
	9	N. P. Jouppi, Architectural and organizational tradeoffs in the design of the MultiTitan CPU, Proceedings of the 16th annual international symposium on Computer architecture, p.281-289, April 1989, Jerusalem, Israel
	10	Nielsen, Michael J. K. Titan System Manual. Tech. Rept. 86/1, Digital Equipment Corporation Western Research Laboratory, September, 1986.
	11	Ousterhout, John. Why Aren't Operating Systems Getting Faster As Fast As Hardware? Tech. Rept. Technote 11, Digital Equipment Corporation Western Research Laboratory, October, 1989.
	12	Smith, Alan J. "Sequential program prefetching in memory hierarchies." IEEE Computer 11, 12 (D~ember 1978), 7-2 i.
	13	Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982 [doi>10.1145/356887.356892]

CITED BY 9

	Kathryn S. McKinley , Olivier Temam, Quantifying loop nest locality using SPEC'95 and the perfect benchmarks, ACM Transactions on Computer Systems (TOCS), v.17 n.4, p.288-336, Nov. 1999
	Gokhan Memik , William H. Mangione-Smith, Increasing power efficiency of multi-core network processors through data filtering, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
	Gokhan Memik , Glenn Reinman , William H. Mangione-Smith, Reducing energy and delay using efficient victim caches, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Ken Batcher , Robert Walker, Cluster miss prediction with prefetch on miss for embedded CPU instruction caches, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
	Robert Cooksey , Stephan Jourdan , Dirk Grunwald, A stateless, content-directed data prefetching mechanism, ACM SIGPLAN Notices, v.37 n.10, October 2002
	Yungang Bao , Mingyu Chen , Yuan Ruan , Li Liu , Jianping Fan , Qingbo Yuan , Bo Song , Jianwei Xu, HMTT: a platform independent full-system memory trace monitoring system, ACM SIGMETRICS Performance Evaluation Review, v.36 n.1, June 2008
	Henry G. Baker, CONS should not CONS its arguments, or, a lazy alloc is a smart alloc, ACM SIGPLAN Notices, v.27 n.3, p.24-34, March 1992
	Timothée Bossart , Alix Munier Kordon , Francis Sourd, Memory management optimization problems for integrated circuit simulators, Discrete Applied Mathematics, v.155 n.14, p.1795-1811, September, 2007
	David Atienza , Praveen Raghavan , José L. Ayala , Giovanni De Micheli , Francky Catthoor , Diederik Verkest , Marisa López-Vallejo, Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures, Integration, the VLSI Journal, v.41 n.1, p.38-48, January, 2008