Memory consistency and event ordering in scalable shared-memory multiprocessors

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Memory consistency and event ordering in scalable shared-memory multiprocessors

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International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents

Barcelona, Spain

Pages: 376 - 387

Year of Publication: 1998

ISBN:1-58113-058-9

Authors

Kourosh Gharachorloo	Computer Systems Laboratory, Stanford University, CA
Daniel Lenoski	Computer Systems Laboratory, Stanford University, CA
James Laudon	Computer Systems Laboratory, Stanford University, CA
Phillip Gibbons	Computer Systems Laboratory, Stanford University, CA
Anoop Gupta	Computer Systems Laboratory, Stanford University, CA
John Hennessy	Computer Systems Laboratory, Stanford University, CA

Sponsors

IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 34, Citation Count: 2

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Sarita Adve and Mark Hill. Personal communication. March 1990.
	2	Forest Baskett, Tom Jermoluk, and Doug Solomon. The 4D-MP graphics superworkstation: Computing + graphics -- 40 MIPS + 40 MFLOPS and 100,000 lighted polygons per second. In Proceedings of the 33rd IEEE Computer Socie~ International Conference - COMPCON 88, pages 468--471, February 1988.
	3	W. C. Brantley, K. P. McAuliffe, and J. Weiss. RP3 processor-memory element. In Proceedings of the 1985 International Conference on Parallel Processing, pages 782-789, 1985.
	4	M. Dubois , C. Scheurich , F. Briggs, Memory access buffering in multiprocessors, Proceedings of the 13th annual international symposium on Computer architecture, p.434-442, June 02-05, 1986, Tokyo, Japan
	5	James R. Goodman. Cache consistency and sequential consistency. Technical Report no. 61, SCI Committee, March 1989.
	6	Anoop Gupta , Milind Tambe , Dirk Kalp , Charles Forgy , Allen Newell, Parallel implementation of OPS5 on the encore multiprocessor: results and analysis, International Journal of Parallel Programming, v.17 n.2, p.95-124, April 1988 [doi>10.1007/BF01383952]
	7	Leslie Lamport. How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Transactions on Computers, C-28(9):241-248, September 1979.
	8	Daniel Lenoski , James Laudon , Kourosh Gharachorloo , Anoop Gupta , John Hennessy, The directory-based cache coherence protocol for the DASH multiprocessor, Proceedings of the 17th annual international symposium on Computer Architecture, p.148-159, May 28-31, 1990, Seattle, Washington, United States
	9	G. F. Pfister, W. C. Brantley, D. A. George, S. L. Harvey, W. J. Kleinfelder, K. P. McAuliffe, E. A. Melton, V. A. Norton, and J. Weiss. The IBM research parallel processor prototype (RP3): introduction and architccm~. In Proceedings of the 1985 International Conference on Parallel Processing, pages 764-77 i, 1985.
	10	C. Scheurich , M. Dubois, Correct memory operation of cache-based multiprocessors, Proceedings of the 14th annual international symposium on Computer architecture, p.234-243, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30377]
	11	C. E. Scheurich, Access ordering and coherence in shared memory multiprocessors, University of Southern California, Los Angeles, CA, 1989
	12	G. E. Schmidt. The Butterfly parallel processor. In Proceedings of the Second International Conference on Supercomputing, pages 362-365, 1987.
	13	Dennis Shasha , Marc Snir, Efficient and correct execution of parallel programs that share memory, ACM Transactions on Programming Languages and Systems (TOPLAS), v.10 n.2, p.282-312, April 1988 [doi>10.1145/42190.42277]

CITED BY 2

	Vadim Iosevich , Assaf Schuster, A comparison of sequential consistency with home-based lazy release consistency for software distributed shared memory, Proceedings of the 18th annual international conference on Supercomputing, June 26-July 01, 2004, Malo, France
	John Giacomoni , John K. Bennett , Antonio Carzaniga , Douglas C. Sicker , Manish Vachharajani , Alexander L. Wolf, Frame shared memory: line-rate networking on commodity hardware, Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems, December 03-04, 2007, Orlando, Florida, USA