On the inclusion properties for multi-level cache hierarchies

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

On the inclusion properties for multi-level cache hierarchies

Full text

Pdf (877 KB)

Source

International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents

Barcelona, Spain

Pages: 345 - 352

Year of Publication: 1998

ISBN:1-58113-058-9

Authors

Jean-Loup Baer	Department of Computer Science, University of Washington, Seattle, WA
Wen-Hann Wang	Department of Computer Science, University of Washington, Seattle, WA

Sponsors

IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 13, Downloads (12 Months): 69, Citation Count: 1

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/285930.285994 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	James Archibald , Jean Loup Baer, An economical solution to the cache coherence problem, Proceedings of the 11th annual international symposium on Computer architecture, p.355-362, January 1984
	2	James Archibald , Jean-Loup Baer, Cache coherence protocols: evaluation using a multiprocessor simulation model, ACM Transactions on Computer Systems (TOCS), v.4 n.4, p.273-298, Nov. 1986 [doi>10.1145/6513.6514]
	3	Baer, J.-L. and W.-H. Wang. Architectural choices for multi-level cache hierarchies. In Proc. 16th International Conference on Parallel Processing, pages 258-2t31, 1987.
	4	Baer,J.-L. and W.-H.Wang. Architectural choices for. multi-level cache hierarchies. Technical Report TR 87- 01-04, University of Washington, January 1987.
	5	Censier,M. and P.Feautrier. A new solution to coherence problems in multicache systems. IEEE TC, C- 27(12):1112-I118, December 11178.
	6	J. H. Chang , H. Chao , K. So, Cache design of a sub-micron CMOS system/370, Proceedings of the 14th annual international symposium on Computer architecture, p.208-213, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30374]
	7	Philip Enslow, Jr., Multiprocessor Organization—a Survey, ACM Computing Surveys (CSUR), v.9 n.1, p.103-129, March 1977 [doi>10.1145/356683.356688]
	8	James R. Goodman, Coherency for multiprocessor virtual address caches, Proceedings of the second international conference on Architectual support for programming languages and operating systems, p.72-81, October 1987, Palo Alto, California, United States
	9	Hattori,A., K~hino, M. and S.Kamimoto. Three-levd hierarchical storage system for FACOM M-380/382. In Proc. Information Processing IFIP, pages 693--697, 1983.
	10	R. H. Katz , S. J. Eggers , D. A. Wood , C. L. Perkins , R. G. Sheldon, Implementing a cache consistency protocol, Proceedings of the 12th annual international symposium on Computer architecture, p.276-283, June 17-19, 1985, Boston, Massachusetts, United States
	11	Chat-Yu Lam , Stuart E. Madnick, Propeties of storage hierarchy systems with multiple page sizes and redundant data, ACM Transactions on Database Systems (TODS), v.4 n.3, p.345-367, Sept. 1979 [doi>10.1145/320083.320095]
	12	Liptay, J. S. Structural aspects of the System/360 model 85 part II - the cache. IBM System Journal, 7(I):15-21, 1968,
	13	Short, R. T. A Study of Multilevel Cache Memories. Muter's Thesis, University of Washington, 1987.
	14	P. Sweazey , A. J. Smith, A class of compatible cache consistency protocols and their support by the IEEE futurebus, Proceedings of the 13th annual international symposium on Computer architecture, p.414-423, June 02-05, 1986, Tokyo, Japan
	15	A. W. Wilson, Jr., Hierarchical cache/bus architecture for shared memory multiprocessors, Proceedings of the 14th annual international symposium on Computer architecture, p.244-252, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30378]
	16	Winsor, D.C. and T.N. Mudge. Crosspoint cache architectures. In Proc. 16th International Conferenoe on Parallel Processing, pages 266-269, 1987.