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Architecture of a message-driven processor
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Source International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents
Barcelona, Spain
Pages: 337 - 344  
Year of Publication: 1998
ISBN:1-58113-058-9
Authors
William J. Dally  Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Linda Chao  Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Andrew Chien  Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Soha Hassoun  Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Waldemar Horwat  Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Jon Kaplan  Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Paul Song  Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Brian Totty  Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Scott Wills  Artificial Intelligence Laboratory and Laboratory for Computer Science, Mssaachusetts Institute of Technology, Cambridge, Massachusetts
Sponsors
IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
Bibliometrics
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Ahuja, $.R., "S/Net: A High Speed Interconnect for Multicomputers," IEEE Jounal on Selected Areas in Commznicationa, November 1983, pp. 751-756.
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Daffy, William J. and Seits, Charles L., "The Torus Routing Chip," ~o appear ~n .L D~trstJuted Sy, tama, Vo|. 1, No. 3, 1986.
 
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Daffy, William J., "Wire Efficient VLSI Mukiprocessor Communication Networks," to appear in Stan/ord Con/e~nce on Advanced i~szarcA in V~SI, 1987.
 
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Intel Scientific Computers, iPSC Umer'J Gu/de, Order No. 175455- 001, San~a Clara, Call/., Aug. 1985.
 
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Inmos Limited, IMS T4~ Reference Manual, Order No. 72 TRN 006 00, Briswl, United Kingdom, November 1984.
 
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Luts, C., et. al., "Duitm of the Monic Element," Proc. MIT Con{evence on Aduanced Remearch in VL.,~I, Artech Books, 1984, pp. 1-10.
 
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Palmer, John F., "The NCUBE Family of Parallel Supercompu~. el's," Proc. IEEE intzrltat~oaai Conference o~ Computer Deeignn ICCD.86, 1980, p. 107.
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Thacker, C.P., ec. el., "Alto: A Persona/Computer," in Computer Strmcturza: Principlem and Ezamplem, Siewiorek, Bell, and Newell, Ed., McGraw Hill, 1982.
 
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Z-80 Product Description, Zilog Corporation, 1977.

Collaborative Colleagues:
William J. Dally: colleagues
Linda Chao: colleagues
Andrew Chien: colleagues
Soha Hassoun: colleagues
Waldemar Horwat: colleagues
Jon Kaplan: colleagues
Paul Song: colleagues
Brian Totty: colleagues
Scott Wills: colleagues