Instruction issue logic for high-performance, interruptable pipelined processors

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Instruction issue logic for high-performance, interruptable pipelined processors

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International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents

Barcelona, Spain

Pages: 329 - 336

Year of Publication: 1998

ISBN:1-58113-058-9

Authors

Gurindar S. Sohi	Computer Sciences Department, University of Wisconsin-Madison, 1210 West Dayton Street, Madison, Wisconsin
Sriram Vajapeyam	Computer Sciences Department, University of Wisconsin-Madison, 1210 West Dayton Street, Madison, Wisconsin

Sponsors

IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	P.M. Kogge, The Archuecture of Pipelined Computers. New York: McGraw-Hill, 1981.
	2	D.W. Anderson, F. J. Sparacio, and R. M. Tomasulo, "The IBM System/360 Model 91: Machine Philosophy and Instruction- Handling," IBM Journal of Research and Development, pp. 8-24, January 1967.
	3	James E. Smith , Andrew R. Pleszkun, Implementation of precise interrupts in pipelined processors, Proceedings of the 12th annual international symposium on Computer architecture, p.36-44, June 17-19, 1985, Boston, Massachusetts, United States
	4	Richard M. Russell, The CRAY-1 computer system, Communications of the ACM, v.21 n.1, p.63-72, Jan. 1978 [doi>10.1145/359327.359336]
	5	James E. Smith, A study of branch prediction strategies, Proceedings of the 8th annual symposium on Computer Architecture, p.135-148, May 12-14, 1981, Minneapolis, Minnesota, United States
	6	J.K.F. Lee and A. J. Smith. "Branch Prediction Strategies and Branch Target Buffer Design," IEEE Computer, vol. 17, pp. 6-22, January 1984.
	7	P. Y T Hsu , E. S. Davidson, Highly concurrent scalar processing, Proceedings of the 13th annual international symposium on Computer architecture, p.386-395, June 02-05, 1986, Tokyo, Japan
	8	A. R. Pleszkun , J. R. Goodman , W. C. Hsu , R. T. Joersz , G. Bier , P. Woest , P. B. Schechter, WISQ: a restartable architecture using queues, Proceedings of the 14th annual international symposium on Computer architecture, p.290-299, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30383]
	9	John Hennessy , Norman Jouppi , Forest Baskett , Thomas Gross , John Gill, Hardware/software tradeoffs for increased performance, Proceedings of the first international symposium on Architectural support for programming languages and operating systems, p.2-11, March 01-03, 1982, Palo Alto, California, United States
	10	R.M. Tomasulo, "'An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal of Research and Development, pp. 25-33, January 1967.
	11	CRAY-1 Computer Systems. llardware Reference Manual. Chippewa Falls, WI: Cray Research. Inc., 1982.
	12	N. Pang and J. E. Smith, "CRAY-1 Simulation Tools," Tech. Report ECE-83-11, University of Wisconsin-Madison, Dec. 1983.
	13	Shlomo Weiss , James E. Smith, Instruction issue logic for pipelined supercomputers, Proceedings of the 11th annual international symposium on Computer architecture, p.110-118, January 1984
	14	F.H. MeMahon, FORTRAN CPU Performance Analysis. Lawrence Livermore Laboratories, 1972.
	15	W. Hwu , Y. N. Patt, HPSm, a high performance restricted data flow architecture having minimal functionality, Proceedings of the 13th annual international symposium on Computer architecture, p.297-306, June 02-05, 1986, Tokyo, Japan