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Memory access buffering in multiprocessors
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Source International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents
Barcelona, Spain
Pages: 320 - 328  
Year of Publication: 1998
ISBN:1-58113-058-9
Authors
Michel Dubois  Computer Research Institute, University of Southern California, Los Angeles, California
Christoph Scheurich  Computer Research Institute, University of Southern California, Los Angeles, California
Faye Briggs  Dept. of Electrical and Computer Eng., Rice University, Houston, Texas
Sponsors
IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 17,   Downloads (12 Months): 137,   Citation Count: 1
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

AND83
 
ARC85
Special session aa commercial cache-based multiprocessors, in the Proceedings of the Igth International Symposium on Computer Architecture, June 1985.
 
BRI79
F.A. Briggs, "Effects of Buffered Memory Requests in Muhiprocessor Systems," Proceedings of t t~e Conference on Simulation, Afeaaurementa, and Modelin9 of Computer Sy:lem~, 1970.
 
BRI83
F.A. Briggs and M. Dubois, "Effectiveness of Private Caches in Muttiprocessors with Parallel-Pipelined Memories," IEEE Transactions on Computers, January 1083.
 
CEN78
L. M. Censier and P. Feautrier,"A New Solution to Coherence Problems in Multicache Systems," IEEE Transactions on Computers, Vol. C-27, No.12, December 1078.
 
CHI84
C-Y Chin and K. Hwang,"Paeket,.switching Networks for Multiprocessor and Data, flow Computers," Proceedings of the ilth International Symposium on Computer Architecture, June 1984.
 
COL84
W. W. Collier, "Architectures for Systems of Parallel Processes," IliA{ Technical Report TR00.3253, January 27. 1984.
 
COL85
W. W. Collier, "Reasoning about Parallel Architectunes," submitted to JACM, 198S.
 
DUB82
M. Dubois and F.A. Briggs, "Effects of Cache Coherency in Multiprocessors," IEEE Transaction: on Computers, Vol. C-31, No. I1, November 1082.
 
GEH82
E.F. Gehringer, etal., "The Cm* Testbed," IEEE Computer, October 1982.
 
HWA84a
 
HWA84b
 
KOG81
 
KRO81
 
KUN76
H.T. Kung, "Synchronized and Asynchronous Parallel Algorithms for multiproeessors," in AOorithms and Complezity: New Directions and Recent Results, J.F. Traub Ed., New York: Academic Press, 1970.
LAM78
 
LAM79
L. Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs," IEEE Transactions on Computers, Vol. C-28, No. 9, September 1079.
PHI83
 
SMI82
A.J. Smith, "Cache Memories," Computing Surveys, Vol. 14, No. 3, September 1082.


Collaborative Colleagues:
Michel Dubois: colleagues
Christoph Scheurich: colleagues
Faye Briggs: colleagues