| Memory access buffering in multiprocessors |
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International Symposium on Computer Architecture
archive
25 years of the international symposia on Computer architecture (selected papers)
table of contents
Barcelona, Spain
Pages: 320 - 328
Year of Publication: 1998
ISBN:1-58113-058-9
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Authors
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Michel Dubois
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Computer Research Institute, University of Southern California, Los Angeles, California
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Christoph Scheurich
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Computer Research Institute, University of Southern California, Los Angeles, California
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Faye Briggs
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Dept. of Electrical and Computer Eng., Rice University, Houston, Texas
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| Bibliometrics |
Downloads (6 Weeks): 17, Downloads (12 Months): 137, Citation Count: 1
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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AND83
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ARC85
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Special session aa commercial cache-based multiprocessors, in the Proceedings of the Igth International Symposium on Computer Architecture, June 1985.
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BRI79
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F.A. Briggs, "Effects of Buffered Memory Requests in Muhiprocessor Systems," Proceedings of t t~e Conference on Simulation, Afeaaurementa, and Modelin9 of Computer Sy:lem~, 1970.
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BRI83
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F.A. Briggs and M. Dubois, "Effectiveness of Private Caches in Muttiprocessors with Parallel-Pipelined Memories," IEEE Transactions on Computers, January 1083.
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CEN78
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L. M. Censier and P. Feautrier,"A New Solution to Coherence Problems in Multicache Systems," IEEE Transactions on Computers, Vol. C-27, No.12, December 1078.
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CHI84
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C-Y Chin and K. Hwang,"Paeket,.switching Networks for Multiprocessor and Data, flow Computers," Proceedings of the ilth International Symposium on Computer Architecture, June 1984.
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COL84
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W. W. Collier, "Architectures for Systems of Parallel Processes," IliA{ Technical Report TR00.3253, January 27. 1984.
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COL85
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W. W. Collier, "Reasoning about Parallel Architectunes," submitted to JACM, 198S.
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DUB82
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M. Dubois and F.A. Briggs, "Effects of Cache Coherency in Multiprocessors," IEEE Transaction: on Computers, Vol. C-31, No. I1, November 1082.
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GEH82
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E.F. Gehringer, etal., "The Cm* Testbed," IEEE Computer, October 1982.
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HWA84a
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HWA84b
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KOG81
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KRO81
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KUN76
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H.T. Kung, "Synchronized and Asynchronous Parallel Algorithms for multiproeessors," in AOorithms and Complezity: New Directions and Recent Results, J.F. Traub Ed., New York: Academic Press, 1970.
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LAM78
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LAM79
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L. Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs," IEEE Transactions on Computers, Vol. C-28, No. 9, September 1079.
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PHI83
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SMI82
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A.J. Smith, "Cache Memories," Computing Surveys, Vol. 14, No. 3, September 1082.
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