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Very long instruction work architectures and the ELI-512
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Source International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents
Barcelona, Spain
Pages: 263 - 273  
Year of Publication: 1998
ISBN:1-58113-058-9
Author
Joseph A. Fisher  Yale University, New Haven, Connecticut
Sponsors
IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 27,   Downloads (12 Months): 46,   Citation Count: 1
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Dasgupta 79
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Fisher 81
J.A. Fisher. Trace scheduling: A technique for global microcode compaction. IEEE Transactions on Computers c-30(7):478-490, July 1981.
 
Foster 72
C.C. Foster and E. M. Riseman. Percolation of code to enhance parallel dispatching and execution. IEEE Transactions on Computers 21(12):1411-1415, December 1972.
Gross 82
Hennessy 82
Jacobs 82
Nicolau 81
 
Padua 80
D.A. Padua, D. J. Kuck, and D. H. Lawrie. High speed multiprocemors and compilation techniques. 1 IEEE Transactions on Computers 29{9):763-776, September 1980.
Patterson 79
 
Patterson 82
D.A. Patterson and C. H. Sequin. A VLSI RISC. Computer 15(9):8-21, SEPT 1982.
 
Riseman 72
E.M. Riseman and C. C. Foster. The inhibition of potential parallelism by conditional jumps. IEEE Transactions on Computers 21(12):1405-1411, December 1972.
 
Tjaden 70
G.S. Tjaden and M. J. Flynn. Detection and parallel execution of independent instructions. IEEE Transactions on Computers 19(10):889-895, October 1970.
Tokoro 78