Lockup-free instruction fetch/prefetch cache organization

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Lockup-free instruction fetch/prefetch cache organization

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International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents

Barcelona, Spain

Pages: 195 - 201

Year of Publication: 1998

ISBN:1-58113-058-9

Author

David Kroft

Control Data Canada, Ltd., Canadian Development Division, Mississauga, Ontario, Canada

Sponsors

IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	C. J. Conti. Concepts of buffer storage,/EEE Computer Group News, 2 (March 1969).
	2	R. M. Meade. How a cache memory enhances a computer's performance, Electronics (Jan. 1972}.
	3	K. R. Kaplan and R. O. Winder. Cache-based computer systems, IEEE Computer (March 1973).
	4	j. Bell, D. Casasent, and C. G. Bell. An investigation of alternative cache organizations. IEEE Transactions on Computers, C- 23 (April 1974).
	5	j. H. Kroeger and R. M. Meade (of Cogar Corporation, Woppingers Fail, NY). Cache buffer memory specification.
	6	A. V. Pohm, O. P. Agrawal, and R. N. Monroe. The cost end performance tradeoffs of buffered memories. Proceedings of the IEE~, 63 (Aug. 1973).
	7	A. J. Smith. Sequential program prefetching in memory hierachies. IEEE Computer (Dec 1978).
	8	G. H. Tools. instruction iookahead and execution traffic considerations for the ~ cache design (Development division internal paper), Control Data-Canada, 1975.