Retrospective: improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers

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Retrospective: improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers

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International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents

Barcelona, Spain

Pages: 71 - 73

Year of Publication: 1998

ISBN:1-58113-058-9

Author

Norman P. Jouppi

Western Research Laboratory, Digital Equipment Corporation, Palo Alto, CA

Sponsors

IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 25, Downloads (12 Months): 47, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Norman P. Jouppi, et. al., "A 300MHz 115W 32b Bipolar ECL Microprocessor," in the IEEE Journal of Solid-State Circuits, November 1993.
	2	Mark Donald Hill , Alan Jay Smith, Aspects of cache memory and instruction buffer performance, 1987
	3	Ehsan Rashid, et. al., "A CMOS RISC CPU with On-Chip Parallel Cache", in the Proceedings of the 1994 International Solid-State Circuits Conference, pages 210-211.
	4	S. Palacharla , R. E. Kessler, Evaluating stream buffers as a secondary cache replacement, Proceedings of the 21ST annual international symposium on Computer architecture, p.24-33, April 18-21, 1994, Chicago, Illinois, United States
	5	K. I. Farkas , N. P. Jouppi , P. Chow, How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors?, Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture, p.78, January 22-25, 1995
	6	Keith I. Farkas , Paul Chow , Norman P. Jouppi , Zvonko Vranesic, Memory-system design considerations for dynamically-scheduled processors, Proceedings of the 24th annual international symposium on Computer architecture, p.133-143, June 01-04, 1997, Denver, Colorado, United States
	7	Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982 [doi>10.1145/356887.356892]