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Retrospective: memory consistency and event ordering in scalable shared-memory multiprocessors
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Source International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents
Barcelona, Spain
Pages: 67 - 70  
Year of Publication: 1998
ISBN:1-58113-058-9
Author
Kourosh Gharachorloo  Western Research Laboratory, Digital Equipment Corporation
Sponsors
IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 12,   Downloads (12 Months): 43,   Citation Count: 1
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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K. Gharachorloo, A. Gupta, and J. Hennessy. Two techniques to enhance the performance of memory consistency models. In Proceedings of the 1991 International Conference on Parallel Processing, pages I:355-364, August 1991.
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K. Gharachorloo, A. Gupta, and J. Hennessy. Revision to "Memory consistency and event ordering in scalable shared-memory multiprocessors". Technical Report CSL-TR-93-568, Stanford University, April 1993.
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Collaborative Colleagues:
Kourosh Gharachorloo: colleagues