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Retrospective: on the inclusion properties for multi-level cache hierarchies
Full text PdfPdf (199 KB)
Source International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents
Barcelona, Spain
Pages: 59 - 60  
Year of Publication: 1998
ISBN:1-58113-058-9
Authors
Jean-Loup Baer  Computer Science & Engineering, University of Washington, Seattle, WA
Wen-Hann Wang  Microcomputer Research Lab, Intel Corp., Hillsboro, OR
Sponsors
IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 12,   Downloads (12 Months): 30,   Citation Count: 1
Additional Information:

references   cited by   index terms   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Jean-Loup Baer , Wen-Hann Wang, Multilevel cache hierarchies: organizations, protocols, and performance, Journal of Parallel and Distributed Computing, v.6 n.3, p.451-476, June 1989  [doi>10.1016/0743-7315(89)90001-4]
2
W. H. Wang , J.-L. Baer , H. M. Levy, Organization and performance of a two-level virtual-real cache hierarchy, Proceedings of the 16th annual international symposium on Computer architecture, p.140-148, April 1989, Jerusalem, Israel
3
Wen-Hann Wang , Jean-Loup Baer, Efficient trace-driven simulation methods for cache performance analysis, ACM Transactions on Computer Systems (TOCS), v.9 n.3, p.222-241, Aug. 1991  [doi>10.1145/128738.128740]
4
N. P. Jouppi , S. J. E. Wilton, Tradeoffs in two-level on-chip caching, Proceedings of the 21ST annual international symposium on Computer architecture, p.34-45, April 18-21, 1994, Chicago, Illinois, United States
5
Tom Lovett , Russell Clapp, STiNG: a CC-NUMA computer system for the commercial marketplace, Proceedings of the 23rd annual international symposium on Computer architecture, p.308-317, May 22-24, 1996, Philadelphia, Pennsylvania, United States
6
A. W. Wilson, Jr., Hierarchical cache/bus architecture for shared memory multiprocessors, Proceedings of the 14th annual international symposium on Computer architecture, p.244-252, June 02-05, 1987, Pittsburgh, Pennsylvania, United States  [doi>10.1145/30350.30378]

CITED BY
Hyunhee Kim , Sungjun Youn , Jihong Kim, A leakage-aware cache sharing technique for low-power chip multi-processors (CMPs) with private L2 caches, Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture, p.30-37, October 26-26, 2008, Toronto, Canada

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES

  K. Computing Milieux
  K.2 HISTORY OF COMPUTING
      Subjects: Hardware


General Terms:
Design, Performance, Theory

Collaborative Colleagues:
Jean-Loup Baer: colleagues
Wen-Hann Wang: colleagues

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