Retrospective: memory access buffering in multiprocessors

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Retrospective: memory access buffering in multiprocessors

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International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents

Barcelona, Spain

Pages: 48 - 50

Year of Publication: 1998

ISBN:1-58113-058-9

Authors

Michel Dubois	Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA
Christoph Scheurich	Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA

Sponsors

IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 16, Downloads (12 Months): 35, Citation Count: 0

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	L.M. Censier and E Feautrier, "A New Solution to Coherence Problems in Multicache Systems," IEEE Transactions on Computers, Vol. C-27, No. 12, pp. 1112-1118, December 1978.
	2	L. Lamport, "How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs," IEEE Transactions on Computers, Vol. C- 28, No. 9, pp. 690-691, September 1979.
	3	W.W. Collier, Architectures for Systems of Parallel Processes, Technical Report TR 00.3253, IBM Corporation, Poughkeepsie, NY, January 1984.
	4	C. Scheurich , M. Dubois, Correct memory operation of cache-based multiprocessors, Proceedings of the 14th annual international symposium on Computer architecture, p.234-243, June 02-05, 1987, Pittsburgh, Pennsylvania, United States [doi>10.1145/30350.30377]
	5	M. Dubois, F.A. Briggs, I. Patil, and M. Balakrishnan, "Trace-driven Simulations of Parallel and Distributed Algorithms in Multiprocessors," Proceedings of the 1986 International Conference on Parallel Processing, August 1986, pp. 909-916.
	6	C. E. Scheurich, Access ordering and coherence in shared memory multiprocessors, University of Southern California, Los Angeles, CA, 1989
	7	Sarita V. Adve , Mark D. Hill, Weak ordering—a new definition, Proceedings of the 17th annual international symposium on Computer Architecture, p.2-14, May 28-31, 1990, Seattle, Washington, United States
	8	Kourosh Gharachorloo , Daniel Lenoski , James Laudon , Phillip Gibbons , Anoop Gupta , John Hennessy, Memory consistency and event ordering in scalable shared-memory multiprocessors, Proceedings of the 17th annual international symposium on Computer Architecture, p.15-26, May 28-31, 1990, Seattle, Washington, United States
	9	Michel Dubois , Christoph Scheurich, Memory Access Dependencies in Shared-Memory Multiprocessors, IEEE Transactions on Software Engineering, v.16 n.6, p.660-673, June 1990 [doi>10.1109/32.55094]
	10	C. Scheurich , M. Dubois, Lockup-free caches in high-performance multiprocessors, Journal of Parallel and Distributed Computing, v.11 n.1, p.25-36, Jan. 1991 [doi>10.1016/0743-7315(91)90068-K]
	11	Fong Pong , Michel Dubois, A New Approach for the Verification of Cache Coherence Protocols, IEEE Transactions on Parallel and Distributed Systems, v.6 n.8, p.773-787, August 1995 [doi>10.1109/71.406955]
	12	Luiz André Barroso , Sasan Iman , Jaeheon Jeong , Koray Öner , Michel Dubois , Krishnan Ramamurthy, RPM: A Rapid Prototyping Engine for Multiprocessor Systems, Computer, v.28 n.2, p.26-34, February 1995 [doi>10.1109/2.347997]