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Retrospective: HPSm, a high performance restricted data flow architecture having minimal functionality
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Source International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents
Barcelona, Spain
Pages: 43 - 44  
Year of Publication: 1998
ISBN:1-58113-058-9
Authors
Wen-mei W. Hwu  Computer & Systems Research Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL
Yale N. Patt  Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI
Sponsors
IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 14,   Downloads (12 Months): 27,   Citation Count: 0
Additional Information:

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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SPARC Programmer's Reference Manual.
 
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G. A. Uvieghara, W. W. Hwu, Y. Nakagome, D. K. Jeong, D. Lee, D. A. Hodges, and Y. N. Patt, "An Experimental Single-Chip Data Flow CPU," Symposium on VLSI Circuits Design, May 1990.

Collaborative Colleagues:
Wen-mei W. Hwu: colleagues
Yale N. Patt: colleagues