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Retrospective: a low-overhead coherence solution for multiprocessors with private cache memories
Full text PdfPdf (310 KB)
Source International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents
Barcelona, Spain
Pages: 39 - 41  
Year of Publication: 1998
ISBN:1-58113-058-9
Author
Janak H. Patel  Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL
Sponsors
IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 17,   Downloads (12 Months): 41,   Citation Count: 0
Additional Information:

references   index terms   collaborative colleagues  

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
Janak H. Patel, Processor-memory interconnections for multiprocessors, Proceedings of the 6th annual symposium on Computer architecture, p.168-177, April 23-25, 1979  [doi>10.1145/800090.802906]
 
2
J. H. Patel, "Performance of processor-memory interconnections for multiprocessors," IEEE Trans. on Computers, vol. C-30, pp. 771-780, Oct. 1981.
3
Edward S. Davidson, A multiple stream microprocessor prototype system: AMP-1, Proceedings of the 7th annual symposium on Computer Architecture, p.9-16, May 06-08, 1980, La Baule, United States  [doi>10.1145/800053.801903]
 
4
M. S. Papamarcos, A low overhead coherence solution for bus-organized multiprocessors with private cache memories, Technical Report CSG-29, University of Illinois at Urbana-Champaign, May 1984.
5
James R. Goodman, Using cache memory to reduce processor-memory traffic, Proceedings of the 10th annual international symposium on Computer architecture, p.124-131, June 13-17, 1983, Stockholm, Sweden

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES

Additional Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

  C. Computer Systems Organization
  C.2 COMPUTER-COMMUNICATION NETWORKS

  K. Computing Milieux
  K.2 HISTORY OF COMPUTING
      Subjects: Hardware


General Terms:
Design, Performance, Standardization, Theory

Collaborative Colleagues:
Janak H. Patel: colleagues

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