Retrospective: using cache memory to reduce processor-memory traffic

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Retrospective: using cache memory to reduce processor-memory traffic

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International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents

Barcelona, Spain

Pages: 32 - 33

Year of Publication: 1998

ISBN:1-58113-058-9

Author

James R. Goodman

Computer Science Department, University of Wisconsin-Madison

Sponsors

IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Doug Burger , James R. Goodman , Alain Kägi, Memory bandwidth limitations of future microprocessors, Proceedings of the 23rd annual international symposium on Computer architecture, p.78-89, May 22-24, 1996, Philadelphia, Pennsylvania, United States
	2	S.J. Frank, "Tightly coupled multiprocessor system speeds memory-access times," Electronics, Vol. 57, No. 1, (january 12, 1984), pp. 164-169.
	3	James R. Goodman, Using cache memory to reduce processor-memory traffic, Proceedings of the 10th annual international symposium on Computer architecture, p.124-131, June 13-17, 1983, Stockholm, Sweden
	4	E. McCreight, "The Dragon computer system: an early overview." TR, Xerox Corp., Sept. 1984.
	5	P. Sweazey , A. J. Smith, A class of compatible cache consistency protocols and their support by the IEEE futurebus, Proceedings of the 13th annual international symposium on Computer architecture, p.414-423, June 02-05, 1986, Tokyo, Japan