Retrospective: an instruction timing model of CPU performance

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Retrospective: an instruction timing model of CPU performance

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International Symposium on Computer Architecture archive
25 years of the international symposia on Computer architecture (selected papers) table of contents

Barcelona, Spain

Pages: 11 - 12

Year of Publication: 1998

ISBN:1-58113-058-9

Authors

Leonard J. Shustek	Network Associates, Inc., Portola Valley, CA
Bernard L. Peuto	Concord Consulting, Portola Valley, CA

Sponsors

IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 1, Downloads (12 Months): 13, Citation Count: 0

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Leonard Jay Shustek, Analysis and performance of computer instruction sets., 1978
	2	H. J. Saal and L. J. Shustek, "On Measuring Computer Systems by Microprogramming," in Microprogramming and Systems Architecture, pp. 473- 490, Infotech Information Ltd, 1975, ISBN 8553- 9220-7.
	3	Bernard L. Peuto, "Architecture of a New Microprocessor", IEEE Computer, V12, #2, February 1979, pp 10-21.
	4	Charles Bass, judy Estrin, Bernard L Peuto, and Gary Prosenko, "Introducing the Z8," Electronics, August 31, 1978.