ACM Home Page
Please provide us with feedback. Feedback
A model for hierarchical memory
Full text PdfPdf (838 KB)
Source Annual ACM Symposium on Theory of Computing archive
Proceedings of the nineteenth annual ACM symposium on Theory of computing table of contents
New York, New York, United States
Pages: 305 - 314  
Year of Publication: 1987
ISBN:0-89791-221-7
Authors
A. Aggarwal  IBM T. J. Watson Research Center, P. O. Box 218, Yorktown Heights, New York
B. Alpern  IBM T. J. Watson Research Center, P. O. Box 218, Yorktown Heights, New York
A. Chandra  IBM T. J. Watson Research Center, P. O. Box 218, Yorktown Heights, New York
M. Snir  IBM T. J. Watson Research Center, P. O. Box 218, Yorktown Heights, New York
Sponsor
SIGACT: ACM Special Interest Group on Algorithms and Computation Theory
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 82,   Citation Count: 41
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/28395.28428
What is a DOI?

ABSTRACT

In this paper we introduce the Hierarchical Memory Model (HMM) of computation. It is intended to model computers with multiple levels in the memory hierarchy. Access to memory location x is assumed to take time ⌈ log x ⌉. Tight lower and upper bounds are given in this model for the time complexity of searching, sorting, matrix multiplication and FFT. Efficient algorithms in this model utilize locality of reference by bringing data into fast memory and using them several times before returning them to slower memory. It is shown that the circuit simulation problem has inherently poor locality of reference. The results are extended to HMM's where memory access time is given by an arbitrary (nondecreasing) function. Tight upper and lower bounds are obtained for HMM's with polynomial memory access time; the algorithms for searching, FFT and matrix multiplication are shown to be optimal for arbitrary memory access time. On-line memory management algorithms for the HMM model are also considered. An algorithm that uses LRU policy at the successive “levels” of the memory hierarchy is shown to be optimal.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

A85
 
Ag86
R. Agarwal, Personal Communication, 1986.
 
AHU74
 
AV86
 
Ba80
I. L. Baer, "Computer Systems Architecture," Computer Science Press, Potomac, MD, 1980.
 
Ch76
C. K. Chow, "Determination of Cache's Capacity and its Matching Storage Hierarchy," iEEE Trans. on Computers, TC-25, No. 2, Feb. 1976, pp. 157-164.
De68
De70
 
HDR80
W. J. }larding, M. H. MacDougall and W. j. Raymond, "Empirical Eslimation of Cache Miss Ratios as a Function of Cache Size," Tech. Report PN 820-420-700S, Amdahl Corp., Sept. 26, 1980.
HK81
 
IBM86
IBM Engineering and Scientific Subroutine Library, Guide and Reference, Program No. 5668-863, SC23-0184-0, Feb. 1986.
 
MC80
C. Mead and L. Conway, introduction to VLSI ~Fxtems, Addison-Wesley, 1980, pg. 316.
 
MGS70
R. L. Mattson, J. Gacsei, D. R. Slutz and I. L. Traiger, "Evaluation Techniques for Storage Hierarchies," IBM Systems Journal, Vol. 9, No. 2, 1970, pp. 78-117.
 
Si83
G. M. Sitberman, "Delayed-Staging Hierarchy Optimization," IEEE Trans. on Computers, TC-32, No. 11, Nov. 1983, pp. 1029-1037.
Sm82
 
Sp78
F. J. Sparacio, "Data Processing System with Second Level Cache," IBM Tech. Disclosure Bulletin, Vol. 21, No. 6, 1978, pp. 2468-2469.
ST85

CITED BY  41

Collaborative Colleagues:
A. Aggarwal: colleagues
B. Alpern: colleagues
A. Chandra: colleagues
M. Snir: colleagues