| A model for hierarchical memory |
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Annual ACM Symposium on Theory of Computing
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Proceedings of the nineteenth annual ACM symposium on Theory of computing
table of contents
New York, New York, United States
Pages: 305 - 314
Year of Publication: 1987
ISBN:0-89791-221-7
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Authors
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A. Aggarwal
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IBM T. J. Watson Research Center, P. O. Box 218, Yorktown Heights, New York
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B. Alpern
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IBM T. J. Watson Research Center, P. O. Box 218, Yorktown Heights, New York
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A. Chandra
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IBM T. J. Watson Research Center, P. O. Box 218, Yorktown Heights, New York
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M. Snir
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IBM T. J. Watson Research Center, P. O. Box 218, Yorktown Heights, New York
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| Bibliometrics |
Downloads (6 Weeks): 5, Downloads (12 Months): 82, Citation Count: 41
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ABSTRACT
In this paper we introduce the Hierarchical Memory Model (HMM) of computation. It is intended to model computers with multiple levels in the memory hierarchy. Access to memory location x is assumed to take time ⌈ log x ⌉. Tight lower and upper bounds are given in this model for the time complexity of searching, sorting, matrix multiplication and FFT. Efficient algorithms in this model utilize locality of reference by bringing data into fast memory and using them several times before returning them to slower memory. It is shown that the circuit simulation problem has inherently poor locality of reference. The results are extended to HMM's where memory access time is given by an arbitrary (nondecreasing) function. Tight upper and lower bounds are obtained for HMM's with polynomial memory access time; the algorithms for searching, FFT and matrix multiplication are shown to be optimal for arbitrary memory access time. On-line memory management algorithms for the HMM model are also considered. An algorithm that uses LRU policy at the successive “levels” of the memory hierarchy is shown to be optimal.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 41
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Richard E. Ladner , James D. Fix , Anthony LaMarca, Cache performance analysis of traversals and random accesses, Proceedings of the tenth annual ACM-SIAM symposium on Discrete algorithms, p.613-622, January 17-19, 1999, Baltimore, Maryland, United States
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Michael A. Bender , Ziyang Duan , John Iacono , Jing Wu, A locality-preserving cache-oblivious dynamic dictionary, Proceedings of the thirteenth annual ACM-SIAM symposium on Discrete algorithms, p.29-38, January 06-08, 2002, San Francisco, California
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Peter A. Buhr , Anil K. Goel , Naomi Nishimura , Prabhakar Ragde, &mgr;Database: parallelism in a memory-mapped environment (research summary), Proceedings of the eighth annual ACM symposium on Parallel algorithms and architectures, p.196-199, June 24-26, 1996, Padua, Italy
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S. W. Hornick , S. R. Maddila , E. P. Mücke , H. Rosenberger , S. S. Skiena , I. G. Tollis, Searching on a Tape, IEEE Transactions on Computers, v.39 n.10, p.1265-1272, October 1990
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Lars Arge , Michael A. Bender , Erik D. Demaine , Bryan Holland-Minkley , J. Ian Munro, Cache-oblivious priority queue and graph algorithm applications, Proceedings of the thiry-fourth annual ACM symposium on Theory of computing, May 19-21, 2002, Montreal, Quebec, Canada
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Guy E. Blelloch , Rezaul A. Chowdhury , Phillip B. Gibbons , Vijaya Ramachandran , Shimin Chen , Michael Kozuch, Provably good multicore cache performance for divide-and-conquer algorithms, Proceedings of the nineteenth annual ACM-SIAM symposium on Discrete algorithms, p.501-510, January 20-22, 2008, San Francisco, California
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