Power exploration for dynamic data types through virtual memory management refinement

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Power exploration for dynamic data types through virtual memory management refinement

Source

International Symposium on Low Power Electronics and Design archive
Proceedings of the 1998 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 311 - 316

Year of Publication: 1998

ISBN:1-58113-059-7

Authors

Julio L. da Silva, Jr.
Francky Catthoor
Diederik Verkest
Hugo de Man

Sponsors

IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): n/a, Downloads (12 Months): n/a, Citation Count: 9

Additional Information:

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ABSTRACT

In this p ap er we pr esent our novelpower exploration methodolo gy for applic ations with dynamic data types. Our methodolo gy is crucial to obtain effe ctive solutions in an emb edded (HW or SW) processor context. The c ontributionsare twofold. First we define the complete search sp ace for Virtual Memory Management (VMM) mechanisms in a structured way with orthogonal de cision tr eesSe condly we present our systematic methodolo gy for explor ation of the maximal power that takes into account characteristics of the application to he avily prune the search space guiding the choies of a VMM mechanism. Finally we demonstrate for two industrial examples that power can vary consider ably dep ending on the VMM chosen. Moreover these exp eriments show the effe ctiveness of our exploration methodolo gy.

CITED BY 9

	Luca Benini , Giovanni De Micheli, System-level power optimization: techniques and tools, Proceedings of the 1999 international symposium on Low power electronics and design, p.288-293, August 16-17, 1999, San Diego, California, United States
	Massoud Pedram, Power optimization and management in embedded systems, Proceedings of the 2001 conference on Asia South Pacific design automation, p.239-244, January 2001, Yokohama, Japan
	P. R. Panda , F. Catthoor , N. D. Dutt , K. Danckaert , E. Brockmeyer , C. Kulkarni , A. Vandercappelle , P. G. Kjeldsberg, Data and memory optimization techniques for embedded systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.2, p.149-206, April 2001
	Alvin R. Lebeck , Xiaobo Fan , Heng Zeng , Carla Ellis, Power aware page allocation, ACM SIGPLAN Notices, v.35 n.11, p.105-116, Nov. 2000
	Alvin R. Lebeck , Xiaobo Fan , Heng Zeng , Carla Ellis, Power aware page allocation, ACM SIGOPS Operating Systems Review, v.34 n.5, p.105-116, Dec. 2000
	Francky Catthoor , Nikil D. Dutt , Christoforos E. Kozyrakis, How to solve the current memory access and data transfer bottlenecks: at the processor architecture or at the compiler level, Proceedings of the conference on Design, automation and test in Europe, p.426-435, March 27-30, 2000, Paris, France
	Sven Wuytack , Julio L. da Silva, Jr. , Francky Catthoor , Gjalt de Jong , Chantal Ykman-Couvreur, Memory management for embedded network applications, Readings in hardware/software co-design, Kluwer Academic Publishers, Norwell, MA, 2001
	Chao Huang , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha, High-level synthesis of distributed logic-memory architectures, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.564-571, November 10-14, 2002, San Jose, California
	Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000