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The energy complexity of register files
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 1998 international symposium on Low power electronics and design table of contents
Monterey, California, United States
Pages: 305 - 310  
Year of Publication: 1998
ISBN:1-58113-059-7
Authors
V. Zyuban  Computer Science & Eng. Department, University of Notre Dame, IN
P. Kogge  Computer Science & Eng. Department, University of Notre Dame, IN
Sponsors
IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 9,   Downloads (12 Months): 61,   Citation Count: 24
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ABSTRACT

Register files (RF) represent a substantial portion of the energy budget in modern processors, and are growing rapidly with the trend towards wider instruction issue. The actual access energy costs depend greatly on the register file circuitry used. This paper compares various RF circuitry techniques for their energy ef- ficiencies, as a function of architectural parameters such as the number of registers and the number of ports. The Port Priority Selection technique was found to be the most energy efficient. The dependence of register file access energy upon technology scaling is also studied. However, as this paper shows, it appears that none of these will be enough to prevent centralized register files from becoming the dominant power component of next-generation superscalar computers, and alternative methods for inter-instruction communication need to be developed. Split register file architecture is analyzed as a possible alternative.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
T. Blalock and R. Jaeger, "A High-Speed Clamped Bit-Line Current-Mode Sense Amplifier", IEEE Journal of Solid-State Circuits, Vol.26, No.4, April 1991.
 
2
K. Farkas, N. Jouppi, P. Chow, "Register File Design Considerations in Dynamically Scheduled Processors." Technical Report 95/10, Digital Equipment Corporation Western Research Lab, November 1995.
 
3
C. Hu, "Future CMOS Scaling and Reliability." Proceedings ofthe IEEE, Vol.81, No.5, May 1993.
 
4
K. Itoh, K. Sasaki and Y. Nakagome, "Trends in Low-Power RAM Circuit Technologies." In: Proceedings of the IEEE, Vol. 83, No.4, April 1995.
 
5
M. Izumikawa and M. Yamashina, "A Current Direction Sense Technique for Multiport SRAM's." IEEE Journal of Solid-State Circuits, Vol.31, No.4, April 1996.
 
6
R. Jolly, "A 9-ns, 1.4-Gigabyte/s, 17-Ported CMOS Register File." IEEE Journal of Solid-State Circuits, Vol.26, No.10, October 1991.
 
7
H. Mizuno and T. Nagano, "Driving Source-Line Cell Architecture for Sub-l-V High-Speed Low-Power Applications." IEEE Journal of Solid-State Circuits, Vol.31, No.4, April 1996.
8
 
9
U.S. Patent No. 5,657,291, issued Aug. 12, 1997 to A. Podlesny, G. Kristovsky, A. Malshin, "Multiport Register File Memory Cell Configuration for Read Operation."
 
10
 
11
V. Zyuban, P. Kogge, "The Energy Complexity of Register Files", Notre Dame CSE Technical Report No.97-20, December 1997.
 
12
V. Zyuban, P. Kogge, "Split Register File Architectures for Inherently Lower Power Microprocessors," In: Power-Driven Microarchitecture Workshop, in conjunction with 1SCA'98, June 1998. available at http://www.cs.colorado.edu/,-., grunwald/LowPowerWorkshop

CITED BY  24