A low power SRAM using auto-backgate-controlled MT-CMOS

ABSTRACT

We have been proposed a low power SRAM using an effective method called “ABC-MT-CMOS” [1]. It controls the backgates to reduce the leakage current when the SRAM is not activated (sleep mode) while retaining the data stored in the memory cells. We also adopted a “CSB Scheme” which clamps both the source lines of the memory cell array and the bit lines. We designed and fabricated test chips containing a 32K-bit gate array SRAM. The experimental results show that the leakage current is reduced to 1/1000 in sleep mode. The active power is 0.27 mW/MHz at 1 V, which is a reduction of 1/12 of a conventional SRAM with a 3.3 V.

REFERENCES

• 1: H. Makino et al., "An Auto-Backgate-Controlled MT- CMOS Circuit", submitted to Sympo. on VLSI Circuits, June 1998.
• 2: T. Kuroda et al., "A 0.9 V 150 MHz 10 mW 4 mm2 2-D Discrete Cosine Transform Core Processor with Variable-Threshold-Voltage Scheme", 1996 Dig. Tech. Papers of ISSCC, pp. 166-167, February 1996.
• 3: S. Mutoh et al., "I-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS ", IEEE JSSC, vol. 30, no. 8, pp. 847-854, August 1995.
• 4: S. Shigematsu, et al., "A I-V high-speed MTCMOS circuit scheme for power-down applications", 1995 Dig. Tech. Papers of Symp. on VLSI Circuits, pp. 125-126, June 1995.
• 5: W. Lee, et al., "A 1 V DSP for Wireless Communications", Dig. Tech. Papers of ISSCC, 1997.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.1 Semiconductor Memories
          Subjects: Static memory (SRAM)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays; Memory technologies
  B.8 Performance and Reliability

  C. Computer Systems Organization

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Experimentation, Measurement, Performance, Theory