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Estimation of maximum power supply noise for deep sub-micron designs
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 1998 international symposium on Low power electronics and design table of contents
Monterey, California, United States
Pages: 233 - 238  
Year of Publication: 1998
ISBN:1-58113-059-7
Authors
Yi-Min Jiang  Dept. of Electrical & Computer Engineering, University of California Santa Barbara, CA
Kwang-Ting Cheng  Dept. of Electrical & Computer Engineering, University of California Santa Barbara, CA
An-Chang Deng  Synopsys, Inc., 700 East Middlefield Road, Mountain View, CA
Sponsors
IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 20,   Citation Count: 10
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ABSTRACT

We propose a new technique for generating a small set of patterns to estimate the maximum power supply noise of deep sub-micron designs. We first build the charge/discharge current and output voltage waveform libraries for each cell, taking power and ground pin characteristics, the power net RC and other input characteristics as parameters. Based on the cells' current and voltage libraries, the power supply noise of a 2-vector sequence can be estimated efficiently by a cell-level waveform simulator. We then apply the Genetic Algorithm based on the efficient waveform simulator to generate a small set of patterns producing high power supply noise. Finally, the results are validated by simulating the obtained patterns using a transistor level simulator. Our experimental results show that the patterns generated by our approach produce a tight lower bound on the maximum power supply noise.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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H. Kriplani, E N. Najm, and I. N. Hajj, "Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution," IEEE Transactions on CAD, pp. 998-1012, August 1995.
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CITED BY  10

Collaborative Colleagues:
Yi-Min Jiang: colleagues
Kwang-Ting Cheng: colleagues
An-Chang Deng: colleagues