| Estimation of maximum power supply noise for deep sub-micron designs |
| Full text |
Pdf
(814 KB)
|
| Source
|
International Symposium on Low Power Electronics and Design
archive
Proceedings of the 1998 international symposium on Low power electronics and design
table of contents
Monterey, California, United States
Pages: 233 - 238
Year of Publication: 1998
ISBN:1-58113-059-7
|
|
Authors
|
|
Yi-Min Jiang
|
Dept. of Electrical & Computer Engineering, University of California Santa Barbara, CA
|
|
Kwang-Ting Cheng
|
Dept. of Electrical & Computer Engineering, University of California Santa Barbara, CA
|
|
An-Chang Deng
|
Synopsys, Inc., 700 East Middlefield Road, Mountain View, CA
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 5, Downloads (12 Months): 20, Citation Count: 10
|
|
|
ABSTRACT
We propose a new technique for generating a small set of patterns to estimate the maximum power supply noise of deep sub-micron designs. We first build the charge/discharge current and output voltage waveform libraries for each cell, taking power and ground pin characteristics, the power net RC and other input characteristics as parameters. Based on the cells' current and voltage libraries, the power supply noise of a 2-vector sequence can be estimated efficiently by a cell-level waveform simulator. We then apply the Genetic Algorithm based on the efficient waveform simulator to generate a small set of patterns producing high power supply noise. Finally, the results are validated by simulating the obtained patterns using a transistor level simulator. Our experimental results show that the patterns generated by our approach produce a tight lower bound on the maximum power supply noise.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
 |
2
|
|
| |
3
|
A.-C. Deng, Y.-C. Shiau, and K.-H. Loh, "Time Domain Current Waveform Simulation of CMOS Circuits," Proceedings of ICCAD, pp. 208-211, November 1988.
|
| |
4
|
|
| |
5
|
GARDS, "Command Reference Manual," Volume 1-4, Silicon Valley Research, September 1996.
|
 |
6
|
Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, K2: an estimator for peak sustainable power of VLSI circuits, Proceedings of the 1997 international symposium on Low power electronics and design, p.178-183, August 18-20, 1997, Monterey, California, United States
[doi> 10.1145/263272.263321]
|
| |
7
|
Y.-M. Jiang, K.-T. Cheng, and A. Krstic, "Estimation of Maximum Power and Instantaneous Current Using a Genetic Algorithm," Proc. of IEEE Custom Integrated Circuits Conference, pp. 135-138, May 1997.
|
| |
8
|
H. Kriplani, E N. Najm, and I. N. Hajj, "Pattern Independent Maximum Current Estimation in Power and Ground Buses of CMOS VLSI Circuits: Algorithms, Signal Correlations, and Their Resolution," IEEE Transactions on CAD, pp. 998-1012, August 1995.
|
 |
9
|
|
| |
10
|
R. Senthinathan and J. L. Prince, Simultaneous Switching Noise of CMOS Devices and Systems, Kluwer Academic Publishers, 1994.
|
| |
11
|
SYNOPSYS, "PowerMill Reference Manual", August 1997.
|
| |
12
|
Ultima Interconnect Technology, Inc., "Ultima-PR User's Guide 2.2.6", 1997.
|
| |
13
|
|
CITED BY 10
|
|
|
|
|
|
|
|
|
|
|
Yi-Min Jiang , Tak K. Young , Kwang-Ting Cheng, VIP—an input pattern generator for indentifying critical voltage drop for deep sub-micron designs, Proceedings of the 1999 international symposium on Low power electronics and design, p.156-161, August 16-17, 1999, San Diego, California, United States
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|