Voltage scheduling problem for dynamically variable voltage processors

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Voltage scheduling problem for dynamically variable voltage processors

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1998 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 197 - 202

Year of Publication: 1998

ISBN:1-58113-059-7

Authors

Tohru Ishihara	Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering, Kyushu University, 6-1 Kasuga-koen, Kasuga-shi, Fukuoka, 816-8580 Japan
Hiroto Yasuura	Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering, Kyushu University, 6-1 Kasuga-koen, Kasuga-shi, Fukuoka, 816-8580 Japan

Sponsors

IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 10, Downloads (12 Months): 84, Citation Count: 161

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper presents a model of dynamically variable voltage processor and basic theorems for power-delay optimization. A static voltage scheduling problem is also proposed and formulated as an integer linear programming (ILP) problem. In the problem, we assume that a core processor can vary its supply voltage dynamically, but can use only a single voltage level at a time. For a given application program and a dynamically variable voltage processor, a voltage scheduling which minimizes energy consumption under an execution time constraint can be found.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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