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System-level power estimation and optimization
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Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 1998 international symposium on Low power electronics and design table of contents
Monterey, California, United States
Pages: 173 - 178  
Year of Publication: 1998
ISBN:1-58113-059-7
Authors
Luca Benini  Hewlett-Packard Laboratories
Robin Hodgson  Hewlett-Packard Laboratories
Polly Siegel  Hewlett-Packard Laboratories
Sponsors
IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 15,   Downloads (12 Months): 53,   Citation Count: 23
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ABSTRACT

Most work to date on power reduction has focused at the component level, not at the system level. In this paper, we propose a framework for describing the power behavior of system-level designs. The model consists of a set of resources, an environmental workload specification, and a power management policy, which serves as the heart of the system model. We map this model to a simulation-based framework to obtain an estimate of the system's power dissipation. Accompanying this, we propose an algorithm to optimize power management policies. The optimization algorithm can be used in a tight loop with the estimation engine to derive new power-management policy algorithms for a given system-level description. We tested our approach by applying it to a real-life low-power portable design, achieving a power estimation accuracy of ∼10%, and a 23% reduction in power after policy optimization.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
R. Golding, P. Bosh et al, "Idleness is not sloth," Proceedings of Winter USENIX Technical Conference, pp. 201-212, Jan. 1995.
 
2
 
3
 
4
J. Rabaey, M. Pedram, Low power design methodologies, Kluwer 1995.
5
 
6
D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," JSSC, vol. 29, no. 6, 663-670, June 1994.
7
 
8
9
 
10
 
11
12
 
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L. Benini, A. Bogliolo, M. Favalli and G. De Micheli, "Regression models for behavioral power estimation," PATMOS, 179-187, Sept. 1996.
 
14
 
15
Maxtor CrystalMax Manual, Part #1354C, 1/21/97.
 
16
lntel Flash Memory Data Manual, Order Number 290151-005, 11/95.
 
17
Sony datasheet: CXK58257AP/ASP/AM-xxL,LL SRAM, 1/93.
 
18
L. Benini, R. Hodgson, and P. Siegel, "System-level power estimation and optimization," HP Labs Technical Report, HPL-98-30, 1998.
 
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CITED BY  23

Collaborative Colleagues:
Luca Benini: colleagues
Robin Hodgson: colleagues
Polly Siegel: colleagues