Low-swing interconnect interface circuits

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Low-swing interconnect interface circuits

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1998 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 161 - 166

Year of Publication: 1998

ISBN:1-58113-059-7

Authors

Hui Zhang	EECS Department, University of California at Berkeley
Jan Rabaey	EECS Department, University of California at Berkeley

Sponsors

IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 40, Citation Count: 14

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ABSTRACT

This paper introduces an energy-efficient FPGA module, intended for embedded implementations. The main features of the proposed cell include a rich local-interconnect network, which drastically reduces the energy dissipated in the wiring, and a dual-voltage scheme that allows pass-transistor networks to operate at low-voltages yet maintain decent performance. Simulations on a benchmark set demonstrate that the proposed module succeeds in its goal of reducing energy consumption by an order of magnitude over existing implementations.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	E. Kusse, Analysis and Circuit Design for Low Power Programmable Logic Modules, M.S. Thesis, UC Berkeley, 1997.
	2	Y. Nakagome et al., "Sub-1-V Swing Intemal Bus Architecture for Future Low-Power ULSI's," IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 414-9, April 1993.
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	5	R. Colshan and B. Jaroun, "A novel reduced swing CMOS BUS interface circuit for high speed low power VLSI systems," Proceedings of lEEE International Symposium on Circuits and Systems, vol. 4, pp. 351-4, 1994.
	6	Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
	7	A.J. Stratakos, High-Efficiency Low-Voltage DC-DC Conversion for Portable Applications, Ph.D. Dissertation, UC Berkeley, 1998.
	8	Dake Liu et al., "Power Consumption Estimation in CMOS VLSI Chips," IEEE J. Solid-State Circuits, vol. 29, No. 6, pp. 663-70, June 1994.
	9	T. Burd, Energy Efficient Processor System Design, Ph.D. Dissertation, UC Berkeley, 1998.

CITED BY 14

	Jatuchai Pangjun , Sachin S. Sapatnekar, Clock distribution using multiple voltages, Proceedings of the 1999 international symposium on Low power electronics and design, p.145-150, August 16-17, 1999, San Diego, California, United States
	Benjamin Bishop , Mary Jane Irwin, Databus charge recovery: practical considerations, Proceedings of the 1999 international symposium on Low power electronics and design, p.85-87, August 16-17, 1999, San Diego, California, United States
	Paul Sotiriadis , Theodoros Konstantakopoulos , Anantha Chandrakasan, Analysis and implementation of charge recycling for deep sub-micron buses, Proceedings of the 2001 international symposium on Low power electronics and design, p.364-369, August 2001, Huntington Beach, California, United States
	Paul P. Sotiriadis , Anantha Chandrakasan, Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Jatuchai Pangjun , Sachin S. Sapatnekar, Low-power clock distribution using multiple voltages and reduced swings, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.309-318, June 2002
	Varghese George , Hui Zhang , Jan Rabaey, The design of a low energy FPGA, Proceedings of the 1999 international symposium on Low power electronics and design, p.188-193, August 16-17, 1999, San Diego, California, United States
	Hua Wang , Antonis Papanikolaou , Miguel Miranda , Francky Catthoor, A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.759-761, January 27-30, 2004, Yokohama, Japan
	Paul P. Sotiriadis , Anantha P. Chandrakasan, A bus energy model for deep submicron technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.341-350, June 2002
	Vasanth Venkatachalam , Michael Franz, Power reduction techniques for microprocessor systems, ACM Computing Surveys (CSUR), v.37 n.3, p.195-237, September 2005
	Monica Donno , Enrico Macii , Luca Mazzoni, Power-aware clock tree planning, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Chun Liu , Anand Sivasubramaniam , Mahmut Kandemir, Optimizing bus energy consumption of on-chip multiprocessors using frequent values, Journal of Systems Architecture: the EUROMICRO Journal, v.52 n.2, p.129-142, February 2006
	Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000
	Ilya Issenin , Nikil Dutt, Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, October 22-25, 2006, Seoul, Korea
	Sungjune Youn , Hyunhee Kim , Jihong Kim, A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches, Proceedings of the 2007 international symposium on Low power electronics and design, August 27-29, 2007, Portland, OR, USA