Low-energy embedded FPGA structures

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Low-energy embedded FPGA structures

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1998 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 155 - 160

Year of Publication: 1998

ISBN:1-58113-059-7

Authors

Eric Kusse	EECS Department, University California at Berkeley, CA
Jan Rabaey	EECS Department, University California at Berkeley, CA

Sponsors

IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 23, Citation Count: 31

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper introduces an energy-efficient FPGA module, intended for embedded implementations. The main features of the proposed cell include a rich local-interconnect network, which drastically reduces the energy dissipated in the wiring, and a dual-voltage scheme that allows pass-transistor networks to operate at low-voltages yet maintain decent performance. Simulations on a benchmark set demonstrate that the proposed module succeeds in its goal of reducing energy consumption by an order of magnitude over existing implementations.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Hauck, S.,et al., "Triptych: An FPGA Architecture with Integrated Logic and Routing", in Advanced Research in VLSI and Parallel Systems: Proceedings of the 1992 Brown/MIT Conference, (March 1992), 26-43.
	2	Kusse, E., "Analysis and Circuit Design for Low Power Programmable Logic Modules", Masters Thesis UC Berkeley, http://infopad.EECS.Berkeley.EDU/ research/reconfigurable/reports/ekusse/thesis.html, (December 1997).
	3	"Motorola chip to combine ColdFire, FPGA cores", htto://techweb.cmo.com/eet/news/98/992news/motorola~,html.
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CITED BY 31

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	Ingrid Verbauwhede , M.-C. Frank Chang, Reconfigurable interconnect for next generation systems, Proceedings of the 2002 international workshop on System-level interconnect prediction, April 06-07, 2002, San Diego, California, USA
	Paul P. Sotiriadis , Anantha P. Chandrakasan, A bus energy model for deep submicron technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.341-350, June 2002
	Paul Sotiriadis , Theodoros Konstantakopoulos , Anantha Chandrakasan, Analysis and implementation of charge recycling for deep sub-micron buses, Proceedings of the 2001 international symposium on Low power electronics and design, p.364-369, August 2001, Huntington Beach, California, United States
	Varghese George , Hui Zhang , Jan Rabaey, The design of a low energy FPGA, Proceedings of the 1999 international symposium on Low power electronics and design, p.188-193, August 16-17, 1999, San Diego, California, United States
	Yan Lin , Fei Li , Lei He, Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Fei Li , Deming Chen , Lei He , Jason Cong, Architecture evaluation for power-efficient FPGAs, Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays, February 23-25, 2003, Monterey, California, USA
	Fei Li , Yan Lin , Lei He , Jason Cong, Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
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	Jason Cong , Yiping Fan , Wei Jiang, Platform-based resource binding using a distributed register-file microarchitecture, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Li Wang , Matthew French , Azadeh Davoodi , Deepak Agarwal, FPGA dynamic power minimization through placement and routing constraints, EURASIP Journal on Embedded Systems, v.2006 n.1, p.7-7, January 2006
	Lilian Bossuet , Guy Gogniat , Jean-Luc Philippe, Communication-oriented design space exploration for reconfigurable architectures, EURASIP Journal on Embedded Systems, v.2007 n.1, p.2-2, January 2007
	Fei Li , Yan Lin , Lei He, Vdd programmability to reduce FPGA interconnect power, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.760-765, November 07-11, 2004
	Lerong Cheng , Yan Lin , Lei He, Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
	Hyeonmin Lim , Kyungsoo Lee , Youngjin Cho , Naehyuck Chang, Flip-flop insertion with shifted-phase clocks for FPGA power reduction, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.335-342, November 06-10, 2005, San Jose, CA
	B. Neumann , T. Sydow , H. Blume , T. G. Noll, Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs, Journal of Signal Processing Systems, v.53 n.1-2, p.129-143, November 2008
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	José C. García , Juan A. Montiel-Nelson , Saeid Nooshabadi, On the design and optimization of symmetric low swing to high swing level converter for on-chip interconnects, Analog Integrated Circuits and Signal Processing, v.60 n.1-2, p.35-42, August 2009
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