ACM Home Page
Please provide us with feedback. Feedback
Emerging power management tools for processor design
Full text PdfPdf (847 KB)
Source International Symposium on Low Power Electronics and Design archive
Proceedings of the 1998 international symposium on Low power electronics and design table of contents
Monterey, California, United States
Pages: 143 - 148  
Year of Publication: 1998
ISBN:1-58113-059-7
Authors
D. T. Blaauw  Motorola, Inc., Austin, TX
A. Dharchoudhury  Motorola, Inc., Austin, TX
R. Panda  Motorola, Inc., Austin, TX
S. Sirichotiyakul  Motorola, Inc., Austin, TX
C. Oh  Motorola, Inc., Austin, TX
T. Edwards  Motorola, Inc., Austin, TX
Sponsors
IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 2,   Downloads (12 Months): 6,   Citation Count: 8
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/280756.280866
What is a DOI?

ABSTRACT

Power management is an increasing concern for processor design. In this paper, we presented an overview of traditional power simulation tools and discussed two emerging power management design technologies: power distribution integrity analysis and standby current measurement and optimization. We present methods for accurate peak current simulation, which is needed for power grid integrity analysis, and discuss the generation and compression of the simulation vectors. Also, static approaches for calculating an upper-bound on the maximum peak current are presented. Standby leakage current is state dependent and we present methods for calculating both the average and maximum leakage current. Finally, optimization methods for minimizing the leakage current by either assigning a standby state to the circuit or by using a dual-Vt process are discussed.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
 
2
 
3
B. George, G. Yeap, M. G. Wloka, S. C. Tyler, and D. Gossain, "Power Analysis for Semi-Custom Design", in Proc. Custom Integrated Circuits Conference, pp. 249-252, May 1994.
 
4
Toas User Manual, Motorola, Inc., 1996.
5
6
7
8
 
9
 
10
S. M. Sze, "Physics of Semiconductor Devices", New- York:John Wiley, 1981.
11
 
12
S. Ercolani, M. Favalli, M. Damiani, P. Olivo, B. Ricco, "Testability Measures in Pseudorandom Testing", in Trans. IEEE Trans. on Computer-Aided Design, pp. 794-800, June 1993.
 
13
J. E Halter and E Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS Circuits", in Proc. Custom Integrated Circuits Conference, 1996.

CITED BY  8

Collaborative Colleagues:
D. T. Blaauw: colleagues
A. Dharchoudhury: colleagues
R. Panda: colleagues
S. Sirichotiyakul: colleagues
C. Oh: colleagues
T. Edwards: colleagues