| Emerging power management tools for processor design |
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International Symposium on Low Power Electronics and Design
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Proceedings of the 1998 international symposium on Low power electronics and design
table of contents
Monterey, California, United States
Pages: 143 - 148
Year of Publication: 1998
ISBN:1-58113-059-7
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Authors
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D. T. Blaauw
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Motorola, Inc., Austin, TX
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A. Dharchoudhury
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Motorola, Inc., Austin, TX
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R. Panda
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Motorola, Inc., Austin, TX
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S. Sirichotiyakul
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Motorola, Inc., Austin, TX
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C. Oh
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Motorola, Inc., Austin, TX
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T. Edwards
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Motorola, Inc., Austin, TX
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Downloads (6 Weeks): 2, Downloads (12 Months): 6, Citation Count: 8
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ABSTRACT
Power management is an increasing concern for processor design. In this paper, we presented an overview of traditional power simulation tools and discussed two emerging power management design technologies: power distribution integrity analysis and standby current measurement and optimization. We present methods for accurate peak current simulation, which is needed for power grid integrity analysis, and discuss the generation and compression of the simulation vectors. Also, static approaches for calculating an upper-bound on the maximum peak current are presented. Standby leakage current is state dependent and we present methods for calculating both the average and maximum leakage current. Finally, optimization methods for minimizing the leakage current by either assigning a standby state to the circuit or by using a dual-Vt process are discussed.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 8
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Gang Qu , Naoyuki Kawabe , Kimiyoshi Usami , Miodrag Potkonjak, Function-level power estimation methodology for microprocessors, Proceedings of the 37th conference on Design automation, p.810-813, June 05-09, 2000, Los Angeles, California, United States
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Siva Narendra , Vivek De , Dimitri Antoniadis , Anantha Chandrakasan , Shekhar Borkar, Scaling of stack effect and its application for leakage reduction, Proceedings of the 2001 international symposium on Low power electronics and design, p.195-200, August 2001, Huntington Beach, California, United States
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Ki-Wook Kim , Seong-Ook Jung , Taewhan Kim , Prashant Saxena , C. L. Liu , Sung-Mo Kang, Coupling delay optimization by temporal decorrelation using dual threshold voltage technique, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.5, p.879-887, October 2003
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N. Vijaykrishnan , Mahmut Kandemir , Mary Jane Irwin , Hyun Suk Kim , Wu Ye , David Duarte, Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework, IEEE Transactions on Computers, v.52 n.1, p.59-76, January 2003
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