Power consumption of parallel spread spectrum correlator architectures

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Power consumption of parallel spread spectrum correlator architectures

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1998 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 133 - 135

Year of Publication: 1998

ISBN:1-58113-059-7

Authors

Won Namgoong	Standford University, Center for Integrated Systems 134
Teresa Meng	Standford University, Center for Integrated Systems 209

Sponsors

IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 15, Citation Count: 2

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ABSTRACT

Parallel correlation in direct-sequence spread spectrum system allows faster and more reliable coarse acquisition. However, the power consumed becomes significant especially for receivers that employ a large number of parallel correlators. In this paper, the power efficiency of various parallel correlator architectures is explored assuming baseband sampled signals of two samples per chip. Active correlators placed in parallel that use both two's complement and sign-magnitude accumulators are first presented. A functionally equivalent M-parallel passive correlators are then studied. In this approach, the baseband sampled signals are passed through a tapped delay-line. Each tap is then multiplied by a stationary reference pseudonoise code and summed using a binary tree network. The passive correlators are generally more power efficient compared to both types of active correlators, especially for large M values. Further reduction in power consumption is possible by splitting the tapped delay-line into even and odd delays and summing using two smaller binary tree adders. This proposed architecture consumes significantly less power compared to all other architectures. The power dissipation of M-parallel correlator architectures are evaluated for M = 8, 16, 32 using TSMC 0.35-µm CMOS technology at 3.3V supply voltage.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Sheng, S. et al., "A low-power CMOS chipset for spread spectrum communications" 1996 Proceedings of the IEEE ISSCC, p 346-347
	2	A. Chandrakasan, Low Power Digital CMOS Design, Ph.D. Thesis, UC Berkeley, Berkeley, CA, 1994
	3	E. Tsern et al., "A low power video-rate pyramid VQ decoder" IEEE JSSC, November 1996

CITED BY 2

	Bibhudatta Sahoo , Martin Kuhlmann , Keshab K. Parhi, A low-power correlator, Proceedings of the 10th Great Lakes symposium on VLSI, p.153-155, March 02-04, 2000, Chicago, Illinois, United States
	Bibhudatta Sahoo , Keshab K. Parhi, A Low Power Correlator for CDMA Wireless Systems, Journal of VLSI Signal Processing Systems, v.35 n.1, p.105-112, August 2003