Partial bus-invert coding for power optimization of system level bus

ABSTRACT

We presen t a partial bus-in vertcoding scheme for po wer optim ization of system level bus. In the proposed sch eme, we select a su b-group of bus lines involved in b us encoding to a void unnecessary inversion of b us lines not in the sub-group thereby redu cing th e total number of bus transitions. We propose a heuristic algorithm that selects the sub-grou p of bus lines for b us encoding. Ex periments on benchmark examples in dicate that the partial bus-in vert coding reduces the tot al bus tran sitions b y 62.6% on the av erage, compared to that of the unencoded patterns.

REFERENCES

• 1: D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE Journal of Solid-State Circuits, vol. 29, pp. 663-670, June 1994.
• 2: Mircea R. Stan , Wayne P. Burleson, Bus-invert coding for low-power I/O, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.1, p.49-58, March 1995 [doi>10.1109/92.365453]
• 3: Luca Benini , Giovanni de Micheli , Enrico Macii , Donatella Sciuto , Cristina Silvano, Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems, Proceedings of the 7th Great Lakes Symposium on VLSI, p.77, March 13-15, 1997
• 4: Luca Benini , Giovanni De Micheli , Enrico Macii , Massimo Poncino , Stefano Quer, System-level power optimization of special purpose applications: the beach solution, Proceedings of the 1997 international symposium on Low power electronics and design, p.24-29, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263277]
• 5: Preeti R. Panda , Nikil D. Dutt, 1995 high level synthesis design repository, Proceedings of the 8th international symposium on System synthesis, p.170-174, September 13-15, 1995, Cannes, France [doi>10.1145/224486.224537]
• 6: S. Lee and W. Sung, "A parser processor for MPEG-2 audio and AC-3 decoding," in Proc. Int'l Symposium on Circuits and Systems, pp. 2621-2624, June 1997.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS
      B.4.3 Interconnections (subsystems)
          Subjects: Topology (e.g., bus, point-to-point)

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

  G. Mathematics of Computing
  G.4 MATHEMATICAL SOFTWARE
      Subjects: Algorithm design and analysis

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Algorithms, Design, Experimentation, Measurement, Performance, Theory