An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors

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An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1998 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 121 - 123

Year of Publication: 1998

ISBN:1-58113-059-7

Authors

Catherine H. Gebotys	Department of Electrical and Computer Engineering, University of Waterloo, Wilfrid Laurier University, Waterloo, Ont, Canada
Robert J. Gebotys

Sponsors

IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 19, Citation Count: 4

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ABSTRACT

This paper presents a comparison of statistically-derived power prediction models at the algorithmic, instruction, and architectural levels for embedded high performance DSP processors. The approach is general enough to be applied to any embedded DSP processor. Results from 168 power measurements of DSP code show that power can be predicted at instruction and architecture levels with less than 2% error. This result is important for developing a general methodology for power characterization of embedded DSP software since low power is critical to complex DSP applications in many cost sensitive markets.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Mike Tien-Chien Lee , Masahiro Fujita , Vivek Tiwari , Sharad Malik, Power analysis and minimization techniques for embedded DSP software, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.1, p.123-135, March 1997 [doi>10.1109/92.555992]
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	3	TMS320C5x User's Guide, Texas Instruments Inc., 1993.
	4	SPSS User's Guide, Base 7.5 for Windows, SPSS Inc, 1997.
	5	Catherine Gebotys, DSP address optimization using a minimum cost circulation technique, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.100-103, November 09-13, 1997, San Jose, California, United States
	6	Catherine H. Gebotys, An efficient model for DSP code generation: performance, code size, estimated energy, Proceedings of the 10th international symposium on System synthesis, p.41-47, September 17-19, 1997, Antwerp, Belgium
	7	G. Gebotys,R.Gebotys, "Statistically Driven Power Prediction Models for DSP Processors",TechRept,ECE,Univ.Waterloo,1998.
	8	Fluke 867B GMM current meter manual, 1997.

CITED BY 4

	Luca Benini , Giovanni De Micheli, System-level power optimization: techniques and tools, Proceedings of the 1999 international symposium on Low power electronics and design, p.288-293, August 16-17, 1999, San Diego, California, United States
	Sheayun Lee , Andreas Ermedahl , Sang Lyul Min, An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors, ACM SIGPLAN Notices, v.36 n.8, p.1-10, Aug. 2001
	Eric Senn , Johann Laurent , Nathalie Julien , Eric Martin, Softexplorer: estimating and optimizing the power and energy consumption of a C program for DSP applications, EURASIP Journal on Applied Signal Processing, v.2005 n.1, p.2641-2654, 1 January 2005
	Young-Hwan Park , Sudeep Pasricha , Fadi J. Kurdahi , Nikil Dutt, Methodology for multi-granularity embedded processor power model generation for an ESL design flow, Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, October 19-24, 2008, Atlanta, GA, USA