0.5 V CMOS logic delivering 200 million 8*8 bit multiplications/s at less than 100 fj based on a 50nm T-gate SOI technology

ABSTRACT

High-performance CMOS logic at a very low voltage of 0.5 V can deliver 150 Million 8x8 multiplications/s at an energy level of only 30fJ, if 0.35 µm SOI technology is enhanced with self-aligned 50 nm T-Gate transistors, if a new adder with a differential Manchester chain including special accelerators and if the DIGILOG multiplier, a leading-one-first pseudo-log multiplier with complexity order (n) are optimized simultaneously.

REFERENCES

• 1: V. Dudek, W. Appel, L. Beer, G. Digele, B. H6ffiinger, "Lithography-Independent Nanometer Silicon MOSFET's on Insulator", IEEE Transactions on Electron Devices ED-43(10), 1996, pp.1626-1632.
• 2: S.J. Abou-Samra, V. Dudek, F. Ayache, A. Guyot, B. Courtois, B. H6ffiinger, "Designing with 3D SOI CMOS", 8th Int. Symposium Silicon-on-Insulator Technology and Devices, Paris Aug.31-Sep. 7,1997.
• 3: V. Dudek, D.O. Keck, G. Mayer, B. H6ffiinger, ,,Digital Consideration for High-Performance, Low- Power Silicon-on-Insulator Gate Arrays", IEEE 1995 Custom Integrated Circuits Conference, p. 2.3.1 - 2.3.4
• 4: B. H6ffiinger, M. Selzer, F. Warkowski, ,,Digital Logarithmic CMOS Multiplier For Very-High-Speed Signal-Processing", IEEE 1991 Custom Integrated Circuits Conference, p. 16.7.1 - 16.7.5

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
  B.8 Performance and Reliability

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Measurement, Performance, Theory