Minimum supply voltage for bulk Si CMOS GSI

ABSTRACT

Limits on energy dissipation are investigated for bulk Si CMOS circuits at each node of the 1997 National Technology Roadmap for Semiconductors (NTRS). Physical, continuous and smooth MOSFET Transregional drain current models that consider high-field effects in scaled devices, and permit trade-offs between saturation drive current and subthreshold leakage current are described and employed to model CMOS circuit performance and power dissipation at low voltages. The Transregional models are used in conjunction with physical threshold voltage roll-off models and stochastic interconnect distributions, at performances, chip sizes and transistor counts forecast by the 1997 NTRS, to project optimal supply and threshold voltages, minimizing total energy dissipated by CMOS logic circuits. Techniques exploiting datapath parallelism to further reduce supply voltage are shown to offer decreasing reductions in power dissipation with technology scaling.

REFERENCES

• 1: The 1997 NTRS, Final Draft, SIA, Dec 1997
• 2: J D Meindl, Proc. IEEE, Vol. 83, No 4 Apr 1995, pg 619.
• 3: J Burr et al, ISSCC Dig Tech Papers, Feb 1994, pp 84-85.
• 4: X. Tang , V. De , J. Meindl, Effects of random MOSFET parameter fluctuations on total power consumption, Proceedings of the 1996 international symposium on Low power electronics and design, p.233-236, August 12-14, 1996, Monterey, California, United States
• 5: A. Bhavnagarwala , V. De , B. Austin , J. Meindl, Circuit techniques for low-power CMOS GSI, Proceedings of the 1996 international symposium on Low power electronics and design, p.193-196, August 12-14, 1996, Monterey, California, United States
• 6: B Agrawal et al, Proc. ESSDERC, Sept 1993, pp 919- 926.
• 7: X Tang, Private Communication
• 8: A Chandrakasan et al, IEEE JSSC Vol 27, No 4, April 1992, pp 473
• 9: J Davis et al, Proc. 46th IEEE ECTC, pp 18.5 May 1996, pp 1002-1008
• 10: R W Keyes, IEEE JSSC, Vol SC-17, Dec 1982, pp 1232-1233
• 11: B Bakoglu, "Circuit Interconnections and Packaging for VLSI", Addison Wesley, 1990
• 12: J Chem et al, IEEE EDL Vol 13, No l, Jan 1992, pg 32.
• 13: R Swanson et aI, IEEE JSSC, Vol. SC-7, pp. 146-153, Apr. 1972
• 14: C Sodini et al, IEEE TED, Vol ED-3 l, No 10, October 1984, pp 1386
• 15: C Jacoboni et al, Solid State Electronics, No 20, Vol 77, 1977
• 16: B Agrawal et al, IEEE TED, Vol 43, No 2, Feb 1996, pg 365
• 17: G Sai Halasz, Proc. of the IEEE, Vol 83, Jan 1995, pp 20-36
• 18: T Sakurai et al, IEEE JSSC, Vol 28, No l, Jan 1993, pg 40

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability

  C. Computer Systems Organization

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Measurement, Performance, Theory