CMOS VCOs for frequency synthesis in wireless biotelemetry

ABSTRACT

A new phase noise model was used to optimize a differential ring VCO for minimum power consumption. We compare the phase noise performance of three buffer stages using clamped, symmetric and cross-coupled loads, respectively. We propose a cross-coupled buffer topology that achieves lower phase noise by exploiting symmetry. Measured phase noise for a 1.2mW, 150MHz VCO fabricated in 0.5µm CMOS is -103.9dBc/Hz at 500KHz offset, showing good agreement with the theory.

REFERENCES

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• 2: A. Hajimiri and T.H. Lee. A General theory of phase noise in electrical oscillators. IEEE JSSC 33, 2 (1998), 179-194.
• 3: J. Maneatis and M. Horowitz. Precise delay generation using coupled oscillators. IEEE JSSC 28, 12 (1993), 1273-1282.
• 4: M. Horowitz, et al. PLL Design for a 500MB/s Interface. ISSCC Digest (1993), 160-161.
• 5: J. Maneatis. Low-Jitter and process-independent DLL and PLL based on self-biased techniques. ISSCC Digest (1996), 130-131,430.
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability

  C. Computer Systems Organization
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Signal processing systems

  I. Computing Methodologies
  I.5 PATTERN RECOGNITION
      I.5.4 Applications
          Subjects: Signal processing

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Measurement, Performance, Theory