The simulation and evaluation of dynamic voltage scaling algorithms

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The simulation and evaluation of dynamic voltage scaling algorithms

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1998 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 76 - 81

Year of Publication: 1998

ISBN:1-58113-059-7

Authors

Trevor Pering	University of California Berkeley Electronics Research Laboratory, 211-109 Cory #1770, Berkeley, CA
Tom Burd	University of California Berkeley Electronics Research Laboratory, 211-109 Cory #1770, Berkeley, CA
Robert Brodersen	University of California Berkeley Electronics Research Laboratory, 211-109 Cory #1770, Berkeley, CA

Sponsors

IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

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ACM New York, NY, USA

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Downloads (6 Weeks): 35, Downloads (12 Months): 121, Citation Count: 132

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

The reduction of energy consumption in microprocessors can be accomplished without impacting the peak performance through the use of dynamic voltage scaling (DVS). This approach varies the processor voltage under software control to meet dynamically varying performance requirements. This paper presents a foundation for the simulation and analysis of DVS algorithms. These algorithms are applied to a benchmark suite specifically targeted for PDA devices.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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