Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors

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Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1998 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 70 - 75

Year of Publication: 1998

ISBN:1-58113-059-7

Authors

Nikolaos Bellas Ibrahim Hajj	Department of Electrical & Computer Engineering and the Coordinated Scince Laboratory, University of Illinois at Urbana-Champaign, 1308 West Main Street, Urbana, IL
George Stamoulis	Department of Electrical & Computer Engineering and the Coordinated Scince Laboratory, University of Illinois at Urbana-Champaign, 1308 West Main Street, Urbana, IL and Intel Corporation, Santa Clara, CA
N. Bellas
C. Polychronopoulos	Department of Electrical & Computer Engineering and the Coordinated Scince Laboratory, University of Illinois at Urbana-Champaign, 1308 West Main Street, Urbana, IL

Sponsors

IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 8, Citation Count: 23

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ABSTRACT

In this paper we propose a technique that uses an additional mini cache located between the I-Cache and the CPU core, and buffers instructions that are nested within loops and are continuously otherwise fetched from the I-Cache. This mechanism is combined with code modifications, through the compiler, that greatly simplify the required hardware, eliminate unnecessary instruction fetching, and consequently reduce signal switching activity and the dissipated energy. We show that the additional cache, dubbed L-Cache, is much smaller and simpler than the I-Cache when the compiler assumes the role of allocating instructions in it. Through simulation, we show that, for the SPECfp95 benchmarks, the I-Cache remains disabled most of the time, and the “cheaper” extra cache is used instead. We present experimental results that validate the effectiveness of this technique, and present the energy gains for most of the SPEC95 benchmarks.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	John H. Edmondson , Paul I. Rubinfeld , Peter J. Bannon , Bradley J. Benschneider , Debra Bernstein , Ruben W. Castelino , Elizabeth M. Cooper , Daniel E. Dever , Dale R. Donchin , Timothy C. Fischer , Anil K. Jain , Shekhar Mehta , Jeanne E. Meyer , Ronald P. Preston , Vidya Rajagopalan , Chandrasekhara Somanathan , Scott A. Taylor , Gilbert M. Wolrich, Internal organization of the Alpha 21164, a 300-MHz 64-bit quad-issue CMOS RISC microprocessor, Digital Technical Journal, v.7 n.1, p.119-135, Jan. 1995
	2	Atul Kalambur , Mary Jane Irwin, An extended addressing mode for low power, Proceedings of the 1997 international symposium on Low power electronics and design, p.208-213, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263336]
	3	V. Tiwari, S. Malik, and A. Wolfe, "Compilation Techniques for Low Energy: An Overview," in Proceedings of the IEEE Symposium on Low Power Electronics, (San Diego, CA), Oct. 1994.
	4	Huzefa Mehta , Robert Michael Owens , Mary Jane Irwin , Rita Chen , Debashree Ghosh, Techniques for low energy software, Proceedings of the 1997 international symposium on Low power electronics and design, p.72-75, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263286]
	5	Vivek Tiwari , Sharad Malik , Andrew Wolfe, Power analysis of embedded software: a first step towards software power minimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.437-445, Dec. 1994 [doi>10.1109/92.335012]
	6	Jui-Ming Chang , Massoud Pedram, Register allocation and binding for low power, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.29-35, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217502]
	7	Catherine H. Gebotys, Low energy memory and register allocation using network flow, Proceedings of the 34th annual conference on Design automation, p.435-440, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266192]
	8	J. Ph. Diguet , S. Wuytack , F. Catthoor , H. De Man, Formalized methodology for data reuse exploration in hierarchical memory mappings, Proceedings of the 1997 international symposium on Low power electronics and design, p.30-35, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263278]
	9	S. Wuytack, F. Catthoor, and H. DeMan, "Transforming Set Data Types to Power Optimal Data Structures," IEEE Transcactions on Computer-Aided Design, vol. 15, pp. 619-629, June 1996.
	10	Raminder S. Bajwa , Mitsuru Hiraki , Hirotsugu Kojima , Douglas J. Gorny , Kenichi Nitta , Avadhani Shridhar , Koichi Seki , Katsuro Sasaki, Instruction buffering to reduce power in processors for signal processing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.5 n.4, p.417-424, Dec. 1997 [doi>10.1109/92.645068]
	11	Johnson Kin , Munish Gupta , William H. Mangione-Smith, The filter cache: an energy efficient memory structure, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.184-193, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	12	Scott McFarling, Procedure merging with instruction caches, Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, p.71-79, June 24-28, 1991, Toronto, Ontario, Canada
	13	Andrew Ayers , Richard Schooler , Robert Gottlieb, Aggressive inlining, Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation, p.134-145, June 16-18, 1997, Las Vegas, Nevada, United States
	14	Alfred V. Aho , Ravi Sethi , Jeffrey D. Ullman, Compilers: principles, techniques, and tools, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1986
	15	S. McFarling, Program optimization for instruction caches, Proceedings of the third international conference on Architectural support for programming languages and operating systems, p.183-191, April 03-06, 1989, Boston, Massachusetts, United States
	16	S. Wilson and N. Jouppi, "An Enhanced Access and Cycle Time Model for On-Chip Caches," DEC WRL Technical Report 93/5, July 1994.
	17	SpeedShop User's Guide. Silicon Graphics Inc., 1996.

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	Tohru Ishihara , Kunihiro Asada, A system level memory power optimization technique using multiple supply and threshold voltages, Proceedings of the 2001 conference on Asia South Pacific design automation, p.456-461, January 2001, Yokohama, Japan
	Alvin R. Lebeck , Xiaobo Fan , Heng Zeng , Carla Ellis, Power aware page allocation, ACM SIGPLAN Notices, v.35 n.11, p.105-116, Nov. 2000
	Tohru Ishihara , Hiroto Yasuura, A power reduction technique with object code merging for application specific embedded processors, Proceedings of the conference on Design, automation and test in Europe, p.617-623, March 27-30, 2000, Paris, France
	Nikolaos Bellas , Ibrahim Hajj , Constantine Polychronopoulos, Using dynamic cache management techniques to reduce energy in a high-performance processor, Proceedings of the 1999 international symposium on Low power electronics and design, p.64-69, August 16-17, 1999, San Diego, California, United States
	Koji Inoue , Tohru Ishihara , Kazuaki Murakami, Way-predicting set-associative cache for high performance and low energy consumption, Proceedings of the 1999 international symposium on Low power electronics and design, p.273-275, August 16-17, 1999, San Diego, California, United States
	David H. Albonesi, Selective cache ways: on-demand cache resource allocation, Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.248-259, November 16-18, 1999, Haifa, Israel
	Emil Talpes , Diana Marculescu, Power reduction through work reuse, Proceedings of the 2001 international symposium on Low power electronics and design, p.340-345, August 2001, Huntington Beach, California, United States
	Gokhan Memik , Glenn Reinman , William H. Mangione-Smith, Reducing energy and delay using efficient victim caches, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Francky Catthoor, Energy-Delay Efficient Data Storage and Transfer Architectures and Methodologies: Current Solutions and Remaining Problems, Journal of VLSI Signal Processing Systems, v.21 n.3, p.219-231, July 1999
	Tom Vander Aa , Murali Jayapala , Francisco Barat , Geert Deconinck , Rudy Lauwereins , Francky Catthoor , Henk Corporaal, Instruction buffering exploration for low energy VLIWs with instruction clusters, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.824-829, January 27-30, 2004, Yokohama, Japan
	Emil Talpes , Diana Marculescu, Impact of technology scaling on energy aware execution cache-based microarchitectures, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Gokhan Memik , William H. Mangione-Smith, Increasing power efficiency of multi-core network processors through data filtering, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France
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	Murali Jayapala , Francisco Barat , Tom Vander Aa , Francky Catthoor , Henk Corporaal , Geert Deconinck, Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors, IEEE Transactions on Computers, v.54 n.6, p.672-683, June 2005
	M. Kandemir , J. Ramanujam , U. Sezer, Improving the energy behavior of block buffering using compiler optimizations, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.1, p.228-250, January 2006
	Luca Benini , Giovanni de Micheli, System-level power optimization: techniques and tools, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.5 n.2, p.115-192, April 2000
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	Tohru Ishihara , Farzan Fallah, A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors, Proceedings of the conference on Design, Automation and Test in Europe, p.358-363, March 07-11, 2005
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