Low load latency through sum-addressed memory (SAM)

ABSTRACT

Load latency contributes significantly to execution time. Because most cache accesses hit, cache-hit latency becomes an important component of expected load latency. Most modern microprocessors have base+offset addressing loads; thus effective cache-hit latency includes an addition as well as the RAM access.This paper introduces a new technique used in the UltraSPARC III microprocessor, Sum-Addressed Memory (SAM), which performs true addition using the decoder of the RAM array, with very low latency. We compare SAM with other methods for reducing the add part of load latency. These methods include sum-prediction with recovery, and bitwise indexing with duplicate-tolerance. The results demonstrate the superior performance of SAM.

REFERENCES

• APS95: Todd M. Austin , Dionisios N. Pnevmatikatos , Gurindar S. Sohi, Streamlining data cache access with fast address calculation, Proceedings of the 22nd annual international symposium on Computer architecture, p.369-380, June 22-24, 1995, S. Margherita Ligure, Italy
• CK94: Bob Cmelik , David Keppel, Shade: a fast instruction-set simulator for execution profiling, Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems, p.128-137, May 16-20, 1994, Nashville, Tennessee, United States
• COR88: Cortadella, J., and J. M. Llaberia. Evaluating A+B=K Conditions in Constant Time. IEEE International Symposium on Circuits and Systems, pages 243-6. 1988.
• COR92: Jordi Cortadella , José M. Llabería, Evaluation of A+B=K Conditions Without Carry Propagation, IEEE Transactions on Computers, v.41 n.11, p.1484-1488, November 1992 [doi>10.1109/12.177318]
• DEC92: DEC Publications, Alpha Architecture Handbook, Special Announcement Edition, DEC, Maynard, M.A. 1992
• HRS+98: Raymond Heald, Ken Shin, Vinita Reddy, I- Feng Kao, Masood Khan, William L. Lynch, Gary Lauterbach, Joe Petolino. 64 KByte Sum-Addressed-Memory Cache with 1.6 ns cycle and 2.6 ns Latency, In ISSCC Proceedings, 1998.
• Kan87: Gerry Kane, mipsR2000 RISC Architecture, Prentic-Hall, Englewood Cliffs, N.J. 1987
• LLP+93: William L. Lynch, Gary Lauterbach, Joe Petolino, Dave Poole. Low-Latency Cache Indexing: XOR and SAM Caches. TechNotes SML193-0350, Sun Microsystems Labs, Inc., 1994.
• OLU92: Kunle Olukotun , Trevor Mudge , Richard Brown, Performance optimization of pipelined primary cache, Proceedings of the 19th annual international symposium on Computer architecture, p.181-190, May 19-21, 1992, Queensland, Australia
• SMI82: Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982 [doi>10.1145/356887.356892]
• WG94: CORPORATE SPARC International, Inc., The SPARC architecture manual (version 9), Prentice-Hall, Inc., Upper Saddle River, NJ, 1994
• WJ94: Steven J. E. Wilton and Norman P. Jouppi. An Enhanced Access and Cycle Time Model for On-Chip Caches, Tech Report 93/5. DEC Western Research Lab. 1994.
• WRP92: Tomohisa Wada, Suresh Rajan, Steven A. Przybylski. An Analytical Access Time Model for On-Chip Cache Memories. IEEE Journal of Solid-State Circuits, Vol. 27, No. 8:1147-1156, Aug., 1992.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Design studies

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES

General Terms:
Design