| Dynamic history-length fitting: a third level of adaptivity for branch prediction |
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International Symposium on Computer Architecture
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Proceedings of the 25th annual international symposium on Computer architecture
table of contents
Barcelona, Spain
Pages: 155 - 166
Year of Publication: 1998
ISBN:0-8186-8491-7
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Authors
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Toni Juan
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Depart. of Computer Architecture, Univ. Politècnica de Catalunya, 08034 Barcelona (Spain)
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Sanji Sanjeevan
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Depart. of Computer Architecture, Univ. Politècnica de Catalunya, 08034 Barcelona (Spain)
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Juan J. Navarro
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Depart. of Computer Architecture, Univ. Politècnica de Catalunya, 08034 Barcelona (Spain)
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IEEE Computer Society
Washington, DC, USA
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Downloads (6 Weeks): 4, Downloads (12 Months): 21, Citation Count: 22
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ABSTRACT
Accurate branch prediction is essential for obtaining high performance in pipelined superscalar processors that execute instructions speculatively. Some of the best current predictors combine a part of the branch address with a fixed amount of global history of branch outcomes in order to make a prediction. These predictors cannot perform uniformly well across all workloads because the best amount of history to be used depends on the code, the input data and the frequency of context switches. Consequently, all predictors that use a fixed history length are therefore unable to perform up to their maximum potential.We introduce a method---called DHLF---that dynamically determines the optimum history length during execution, adapting to the specific requirements of any code, input data and system workload. Our proposal adds an extra level of adaptivity to two-level adaptive branch predictors. The DHLF method can be applied to any one of the predictors that combine global branch history with the branch address. We apply the DHLF method to gshare (dhlf-gshare) and obtain near-optimal results for all SPECint95 benchmarks, with and without context switches. Some results are also presented for gskewed (dhlf-gskewed), confirming that other predictors can benefit from our proposal.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 22
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Alexandre Farcy , Olivier Temam , Roger Espasa , Toni Juan, Dataflow analysis of branch mispredictions and its application to early resolution of branch outcomes, Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture, p.59-68, November 1998, Dallas, Texas, United States
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Amirali Baniasadi , Andreas Moshovos, Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.337-347, December 2000, Monterey, California, United States
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Alexander V. Veidenbaum , Weiyu Tang , Rajesh Gupta , Alexandru Nicolau , Xiaomei Ji, Adapting cache line size to application behavior, Proceedings of the 13th international conference on Supercomputing, p.145-154, June 20-25, 1999, Rhodes, Greece
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Roni Rosner , Micha Moffie , Yiannakis Sazeides , Ronny Ronen, Selecting long atomic traces for high coverage, Proceedings of the 17th annual international conference on Supercomputing, June 23-26, 2003, San Francisco, CA, USA
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