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Switcherland: a QoS communication architecture for workstation clusters
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Source International Symposium on Computer Architecture archive
Proceedings of the 25th annual international symposium on Computer architecture table of contents
Barcelona, Spain
Pages: 98 - 108  
Year of Publication: 1998
ISBN:0-8186-8491-7
Also published in ...
Authors
Hans Eberle  Swiss Federal Institute of Technology (ETH), CH-8092 Zurich, Switzerland
Erwin Oertli  Swiss Federal Institute of Technology (ETH), CH-8092 Zurich, Switzerland
Sponsors
IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
IEEE Computer Society  Washington, DC, USA
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ABSTRACT

Computer systems have become powerful enough to process continuous data streams such as video or animated graphics. While processing power and communication bandwidth of today's systems typically are sufficient, quality of service (QoS) guarantees as required for handling such data types cannot be provided by these systems in adequate ways.We present Switcherland, a scalable communication architecture based on crossbar switches that provides QoS guarantees for workstation clusters in the form of reserved bandwidth and bounded transmission delays. Similar to the ATM technology Switcherland provides QoS guarantees with the help of service classes, that is, data transfers are characterized as variable bit rate traffic or constant bit rate traffic. However, unlike LAN technologies, Switcherland is optimized for cluster computing in that (i) it serves as a backplane interconnection fabric as well as a LAN, (ii) it extends support for service classes by also covering the end nodes of the network, (iii) it provides low latency in the order of one microsecond per switch, and (iv) it uses a communication model based on a global memory to simplify programming.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
T. Anderson, S. Owicki, J. Saxe, C. Thacker. High Speed Switch Scheduling for Local Area Networks. Report no. 99, Digital Equipment Corporation, Systems Research Center, April 1993.
 
2
G. Babic, A. Durresi, R. Jain, J. Dolske, S. Shahpurwala. ATM Switch Performance Testing Experiences, ATM Forum/97-O 178R 1, April 1997, http://www.cis.ohio-state.edu/--j ain/atmf/a-0178r I .htm.
 
3
 
4
M. Galles. Scalable Pipelined Interconnect for Distributed Endpoint Routing - The SGI Spider Chip, Silicon Graphics, White Paper, 1996, http://www.sgi.com/ Technology/spider_paper/spider_paper.html.
 
5
6
 
7
 
8
M. Karol, M. Hluchyi, S. Morgan. Input versus Output Queuing on a Space-Division Packet Switch. IEEE Transactions on Communications, C-35(12):1347-1356, December 1987.
 
9
M. Katevenis. Telegraphos: High-Speed Communications Architecture for Parallel and Distributed Computer Systems. Technical Report 123, Foundation for Research and Technology, Heraklio, Crete, 1994.
 
10
H. Kung, R. Morris. Credit-Based Flow Control for ATM Networks. IEEE Network, 40-48, March/April 1995.
 
11
 
12
 
13
 
14
A. Widmer, P. Franaszek. A DC-Balalanced, Partitioned- Block, 8B/lOB Transmission Code. IBM Journal of Research and Development, 27(5):440-451, September 1983.
 
15
K. Ramakrishnan, P. Newman. Integration of Rate and Credit Schemes for ATM Flow Control. IEEE Network, 49- 56, March/April 1995.


Collaborative Colleagues:
Hans Eberle: colleagues
Erwin Oertli: colleagues