| Multi-level texture caching for 3D graphics hardware |
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International Symposium on Computer Architecture
archive
Proceedings of the 25th annual international symposium on Computer architecture
table of contents
Barcelona, Spain
Pages: 86 - 97
Year of Publication: 1998
ISBN:0-8186-8491-7
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Authors
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Michael Cox
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MRJ/NASA Ames Research Center, Moffett Field, CA and Intel Microcomputer Research Labs, 2200 Mission College Blvd., Santa Clara, CA
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Narendra Bhandari
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Intel Microcomputer Research Labs, 2200 Mission College Blvd., Santa Clara, CA
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Michael Shantz
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Intel Microcomputer Research Labs, 2200 Mission College Blvd., Santa Clara, CA
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IEEE Computer Society
Washington, DC, USA
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Downloads (6 Weeks): 16, Downloads (12 Months): 51, Citation Count: 9
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ABSTRACT
Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval of texture during rasterization, and the application is responsible for managing this memory. The push architecture has a bandwidth advantage, but disadvantages of limited texture capacity, escalation of accelerator memory requirements (and therefore cost), and poor memory utilization. The push architecture also requires the programmer to solve the bin- packing problem of managing accelerator memory each frame. More recently graphics hardware on PC-class machines has moved to an implementation of what we call the pull architecture. Texture is stored in system memory and downloaded by the accelerator as needed. The pull architecture has advantages of texture capacity, stems the escalation of accelerator memory requirements, and has good memory utilization. It also frees the programmer from accelerator texture memory management. However, the pull architecture suffers escalating requirements for bandwidth from main memory to the accelerator. In this paper we propose multi-level texture caching to provide the accelerator with the bandwidth advantages of the push architecture combined with the capacity advantages of the pull architecture. We have studied the feasibility of 2-level caching and found the following: (1) significant re-use of texture between frames; (2) L2 caching requires significantly less memory than the push architecture; (3) L2 caching requires significantly less bandwidth from host memory than the pull architecture; (4) L2 caching enables implementation of smaller L1 caches that would otherwise bandwidth-limit accelerators on the workloads in this paper. Results suggest that an L2 cache achieves the original advantage of the pull architecture --- stemming the growth of local texture memory --- while at the same time stemming the current explosion in demand for texture bandwidth between host memory and the accelerator.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CITED BY 9
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Homan Igehy , Matthew Eldridge , Pat Hanrahan, Parallel texture caching, Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware, p.95-106, August 08-09, 1999, Los Angeles, California, United States
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B. V. N. Silpa , Anjul Patney , Tushar Krishna , Preeti Ranjan Panda , G. S. Visweswaran, Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors, Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design, November 10-13, 2008, San Jose, California
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