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Performance characterization of a Quad Pentium Pro SMP using OLTP workloads
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Source International Symposium on Computer Architecture archive
Proceedings of the 25th annual international symposium on Computer architecture table of contents
Barcelona, Spain
Pages: 15 - 26  
Year of Publication: 1998
ISBN:0-8186-8491-7
Also published in ...
Authors
Kimberly Keeton  Computer Science Division, University of California at Berkeley, 387 Soda Hall #1776, Berkeley, CA
David A. Patterson  Computer Science Division, University of California at Berkeley, 387 Soda Hall #1776, Berkeley, CA
Yong Qiang He  Informix Software, Inc., 4100 Bohannon Drive, Menlo Park, CA
Roger C. Raphael  Informix Software, Inc., 4100 Bohannon Drive, Menlo Park, CA
Walter E. Baker  Informix Software, Inc., 4100 Bohannon Drive, Menlo Park, CA
Sponsors
IEEE-CS\TCCA : TC on Computer Arhitecture
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
IEEE Computer Society  Washington, DC, USA
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Downloads (6 Weeks): 11,   Downloads (12 Months): 30,   Citation Count: 60
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ABSTRACT

Commercial applications are an important, yet often overlooked, workload with significantly different characteristics from technical workloads. The potential impact of these differences is that computers optimized for technical workloads may not provide good performance for commercial applications, and these applications may not fully exploit advances in processor design. To evaluate these issues, we use hardware counters to measure architectural features of a four-processor Pentium Pro-based server running a TPC-C-like workload on an Informix database. We examine the effectiveness of out-of-order execution, branch prediction, speculative execution, superscalar issue and retire, caching and multiprocessor scaling. We find that out-of-order execution, superscalar issue and retire, and branch prediction are not as effective for database workloads as they are for technical workloads, such as SPEC. We find that caches are effective at reducing processor traffic to memory; even larger caches would be helpful to satisfy more data requests. Multiprocessor scaling of this workload is good, but even modest bus utilization degrades application memory latency, limiting database throughput.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
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CITED BY  60

Collaborative Colleagues:
Kimberly Keeton: colleagues
David A. Patterson: colleagues
Yong Qiang He: colleagues
Roger C. Raphael: colleagues
Walter E. Baker: colleagues