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RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns

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International Conference on Hardware Software Codesign archive
Proceedings of the 6th international workshop on Hardware/software codesign table of contents

Seattle, Washington, United States

Pages: 139 - 143

Year of Publication: 1998

ISBN:0-8186-8442-9

Authors

Karam S. Chatha	Department of ECECS, University of Cincinnati, Cincinnati, Ohio
Ranga Vemuri	Department of ECECS, University of Cincinnati, Cincinnati, Ohio

Sponsors

SIGSOFT: ACM Special Interest Group on Software Engineering
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 7, Citation Count: 4

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	P. Calland. A. Darte and Y. Robert, "A new guaranteed heuristic for the software pipelining problem," Research Report No. 2759, INRIA, France, December 1995.
	3	B. Fluiter, E.H.L. Aarts, J.H.>I. Korst, W.F.J. Verhaegh and A.V.D. Werf, "The complexity of Generalised Retiming Problem," IEEE Transacttons on Computer-Atded Desrgn of Integrated Carcults and Systems, Vol. 15, No. 11. November 1996.
	4	S. Huang and J. Rabaey, "Maximizing the Throughput of High Performance DSP Applications using Behavioral Transformations," Proceedmgs of EDAC-ETC-EUROASIC '94, pp 25-40, March 1994.
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	6	C. E. Leiserson and J. B. Saxe, "Retiming Synchronous Circuitry," Algortthmtca, vol. 6, no. 1, pp. 5-35, 1991.
	7	S. Malik, K.J. Singh, R.K. Brayton and A. Sangiovanni-Vincentelli, " Performance Optimization of Pipelined Logic Circuits Using Peripheral Retiming and Resynthesis," IEEE Transactrons on Computer-A:ded Desrgn of Integrated Cwcuzts and Systems. Vol 12. No. 5, .May 1993.
	8	William B. Pennebaker , Joan L. Mitchell, JPEG Still Image Data Compression Standard, Kluwer Academic Publishers, Norwell, MA, 1992
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	11	Michael Sheliga , Nelson Luiz Passos , Edwin Hsing-Mean S' ha, Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications, Proceedings of the 4th International Workshop on Hardware/Software Co-Design, p.18, March 18-20, 1996
	12	Jeffrey Walrath, Performance Modeling and Tradeoff Analysis During Rapid Prototyping, Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, p.313, August 19-23, 1996

CITED BY 4

	Karam S. Chatha , Ranga Vemuri, MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs, Proceedings of the ninth international symposium on Hardware/software codesign, p.42-47, April 2001, Copenhagen, Denmark
	Timothy W. O'Neil , Edwin H.-M. Sha, Combining extended retiming and unfolding for rate-optimal graph transformation, Journal of VLSI Signal Processing Systems, v.39 n.3, p.273-293, March 2005
	Karam S. Chatha , Ranga Vemuri, A tool for partitioning and pipelined scheduling of hardware-software systems, Proceedings of the 11th international symposium on System synthesis, p.145-151, December 02-04, 1998, Hsinchu, Taiwan, China
	Timothy W. O'Neil , Edwin H.-M. Sha, Combining Extended Retiming and Unfolding for Rate-Optimal Graph Transformation, Journal of VLSI Signal Processing Systems, v.39 n.3, p.273-293, March 2005