A case study on modeling shared memory access effects during performance analysis of HW/SW systems

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A case study on modeling shared memory access effects during performance analysis of HW/SW systems

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International Conference on Hardware Software Codesign archive
Proceedings of the 6th international workshop on Hardware/software codesign table of contents

Seattle, Washington, United States

Pages: 117 - 121

Year of Publication: 1998

ISBN:0-8186-8442-9

Authors

Marcello Lajolo	Politecnico di Torino, Torino, Italy and NEC C&C Research Labs, Princeton, NJ
Anand Raghunathan	NEC C&C Research Labs, Princeton, NJ
Sujit Dey	UC San Diego, La Jolla, CA and NEC C&C Research Labs, Princeton, NJ
Luciano Lavagno	Politecnico di Torino, Torino, Italy
Alberto Sangiovanni-Vincentelli	University of California at Berkeley, Berkeley, CA

Sponsors

SIGSOFT: ACM Special Interest Group on Software Engineering
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 17, Citation Count: 8

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 8

	Abhijit K. Deb , Johnny Öberg , Axel Jantsch, Control and communication performance analysis of embedded DSP systems in the MASIC methodology, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Sungjoo Yoo , Kyoungseok Rha , Youngchul Cho , Jinyong Jung , Kiyoung Choi, Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model, Proceedings of the eighth international workshop on Hardware/software codesign, p.77-81, May 2000, San Diego, California, United States
	Marcello Lajolo , Anand Raghunathan , Sujit Dey, Efficient power co-estimation techniques for system-on-chip design, Proceedings of the conference on Design, automation and test in Europe, p.27-34, March 27-30, 2000, Paris, France
	Jong-Yeol Lee , In-Cheol Park, Timed compiled-code simulation of embedded software for performance analysis of SOC design, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Kanishka Lahiri , Anand Raghunathan , Sujit Dey, Fast performance analysis of bus-based system-on-chip communication architectures, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.566-573, November 07-11, 1999, San Jose, California, United States
	Marcello Lajolo, Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.974-982, 12/1/2001
	Marcello Lajolo , Anand Raghunathan , Sujit Dey , Luciano Lavagno, Cosimulation-based power estimation for system-on-chip design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.253-266, June 2002
	Abhijit K. Deb , Johnny Oberg , Axel Jantsch, Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology, Proceedings of the conference on Design, Automation and Test in Europe, p.11100, March 03-07, 2003