Utilizing reuse information in data cache management

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Utilizing reuse information in data cache management

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International Conference on Supercomputing archive
Proceedings of the 12th international conference on Supercomputing table of contents

Melbourne, Australia

Pages: 449 - 456

Year of Publication: 1998

ISBN:0-89791-998-X

Authors

Jude A. Rivers	Advanced Computer Architecture Laboratory, The University of Michigan, Ann Arbor, Michigan
Edward S. Tam	Advanced Computer Architecture Laboratory, The University of Michigan, Ann Arbor, Michigan
Gary S. Tyson	Advanced Computer Architecture Laboratory, The University of Michigan, Ann Arbor, Michigan
Edward S. Davidson	Advanced Computer Architecture Laboratory, The University of Michigan, Ann Arbor, Michigan
Matt Farrens	Dept. of Computer Science, University of California at Davis, Davis, California

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 20, Citation Count: 15

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	David Kroft, Lockup-free instruction fetch/prefetch cache organization, Proceedings of the 8th annual symposium on Computer Architecture, p.81-87, May 12-14, 1981, Minneapolis, Minnesota, United States
	3	Jean-Loup Baer , Tien-Fu Chen, An effective on-chip preloading scheme to reduce data access penalty, Proceedings of the 1991 ACM/IEEE conference on Supercomputing, p.176-186, November 18-22, 1991, Albuquerque, New Mexico, United States [doi>10.1145/125826.125932]
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	6	Gary Tyson , Matthew Farrens , John Matthews , Andrew R. Pleszkun, A modified approach to data cache management, Proceedings of the 28th annual international symposium on Microarchitecture, p.93-103, November 29-December 01, 1995, Ann Arbor, Michigan, United States
	7	J.A. Rivers and E.S. Davidson, "Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design," Proceedings of the 1996 ICPP, pp. 154-163, August 1996.
	8	Teresa L. Johnson , Wen-mei W. Hwu, Run-time adaptive cache hierarchy management via reference analysis, Proceedings of the 24th annual international symposium on Computer architecture, p.315-326, June 01-04, 1997, Denver, Colorado, United States
	9	Norman P. Jouppi, Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, ACM SIGARCH Computer Architecture News, v.18 n.3a, p.364-373, June 1990
	10	D. Burger and T. M. Austin, "Evaluating Future Microprocessors: the SimpleScalar Tool Set," Tech. Report #1342, University of Wisconsin, June 1997.
	11	Antonio González , Carlos Aliagas , Mateo Valero, A data cache with multiple caching strategies tuned to different types of locality, Proceedings of the 9th international conference on Supercomputing, p.338-347, July 03-07, 1995, Barcelona, Spain [doi>10.1145/224538.224622]
	12	Chih-Chieh Lee , I-Cheng K. Chen , Trevor N. Mudge, The bi-mode branch predictor, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.4-13, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	13	E. Tam , J. Rivers , G. Tyson , E. Davidson, mlcache: A Flexible Multi-Lateral Cache Simulator, Proceedings of the 6th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, p.19, July 19-24, 1998

CITED BY 15

	Edward S. Tam , Jude A. Rivers , Vijayalakshmi Srinivasan , Gary S. Tyson , Edward S. Davidson, Active Management of Data Caches by Exploiting Reuse Information, IEEE Transactions on Computers, v.48 n.11, p.1244-1259, November 1999
	Jesús Sánchez , Antonio González, A locality sensitive multi-module cache with explicit management, Proceedings of the 13th international conference on Supercomputing, p.51-59, June 20-25, 1999, Rhodes, Greece
	Julio Sahuquillo , Ana Pont, Splitting the Data Cache: A Survey, IEEE Concurrency, v.8 n.3, p.30-35, July 2000
	Soontae Kim , N. Vijaykrishnan , Mahmut Kandemir , Anand Sivasubramaniam , Mary Jane Irwin, Partitioned instruction cache architecture for energy efficiency, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.2, p.163-185, May 2003
	Hans Vandierendonck , Koen De Bosschere, Highly accurate and efficient evaluation of randomising set index functions, Journal of Systems Architecture: the EUROMICRO Journal, v.48 n.13-15, p.429-452, May 2003
	Chi-Hung Chi , Jun-Li Yuan , Chin-Ming Cheung, Cyclic dependence based data reference prediction, Proceedings of the 13th international conference on Supercomputing, p.127-134, June 20-25, 1999, Rhodes, Greece
	Teresa L. Johnson , Daniel A. Connors , Matthew C. Merten , Wen-mei W. Hwu, Run-Time Cache Bypassing, IEEE Transactions on Computers, v.48 n.12, p.1338-1354, December 1999
	Aviral Shrivastava , Ilya Issenin , Nikil Dutt, Compilation techniques for energy reduction in horizontally partitioned cache architectures, Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, September 24-27, 2005, San Francisco, California, USA
	Rong Xu , Zhiyuan Li, A sample-based cache mapping scheme, ACM SIGPLAN Notices, v.40 n.7, July 2005
	Kyoungwoo Lee , Aviral Shrivastava , Ilya Issenin , Nikil Dutt , Nalini Venkatasubramanian, Mitigating soft error failures for multimedia applications by selective data protection, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, October 22-25, 2006, Seoul, Korea
	Zhiyuan Li , Rong Xu, Page mapping for heterogeneously partitioned caches: Complexity and heuristics, Journal of Embedded Computing, v.1 n.4, p.471-485, December 2005
	Aviral Shrivastava , Ilya Issenin , Nikil Dutt, A compiler-in-the-loop framework to explore horizontally partitioned cache architectures, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Haakon Dybdahl , Per Stenström , Lasse Natvig, An LRU-based replacement algorithm augmented with frequency of access in shared chip-multiprocessor caches, ACM SIGARCH Computer Architecture News, v.35 n.4, September 2007
	Haiming Liu , Michael Ferdman , Jaehyuk Huh , Doug Burger, Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.222-233, November 08-12, 2008
	Chuanjun Zhang , Bing Xue, Divide-and-conquer: a bubble replacement for low level caches, Proceedings of the 23rd international conference on Supercomputing, June 08-12, 2009, Yorktown Heights, NY, USA