Characterization and improvement of load/store cache-based prefetching

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Characterization and improvement of load/store cache-based prefetching

Full text

Pdf (1.16 MB)

Source

International Conference on Supercomputing archive
Proceedings of the 12th international conference on Supercomputing table of contents

Melbourne, Australia

Pages: 369 - 376

Year of Publication: 1998

ISBN:0-89791-998-X

Authors

Pablo Ibáñez	Depto. Informática e Ing. de Sistemas, Univ. Zaragoza, c/ Ma. de Luna, 3 - 50015 ZARAGOZA, Spain
Víctor Viñals	Depto. Informática e Ing. de Sistemas, Univ. Zaragoza, c/ Ma. de Luna, 3 - 50015 ZARAGOZA, Spain
José L. Briz	Depto. Informática e Ing. de Sistemas, Univ. Zaragoza, c/ Ma. de Luna, 3 - 50015 ZARAGOZA, Spain
María J. Garzarán	Depto. Informática e Ing. de Sistemas, Univ. Zaragoza, c/ Ma. de Luna, 3 - 50015 ZARAGOZA, Spain

Sponsors

SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 10, Citation Count: 3

Additional Information:

references cited by index terms collaborative colleagues

Tools and Actions:	Request Permissions Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/277830.277921 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Jean-Loup Baer , Tien-Fu Chen, An effective on-chip preloading scheme to reduce data access penalty, Proceedings of the 1991 ACM/IEEE conference on Supercomputing, p.176-186, November 18-22, 1991, Albuquerque, New Mexico, United States [doi>10.1145/125826.125932]
	2	Keith Boland , Apostolos Dollas, Predicting and Precluding Problems with Memory Latency, IEEE Micro, v.14 n.4, p.59-67, August 1994 [doi>10.1109/40.296166]
	3	Doug Burger , James R. Goodman , Alain Kägi, Memory bandwidth limitations of future microprocessors, Proceedings of the 23rd annual international symposium on Computer architecture, p.78-89, May 22-24, 1996, Philadelphia, Pennsylvania, United States
	4	T.-F. Chen , J.-L. Baer, A performance study of software and hardware data prefetching schemes, Proceedings of the 21ST annual international symposium on Computer architecture, p.223-232, April 18-21, 1994, Chicago, Illinois, United States
	5	Bob Cmelik , David Keppel, Shade: a fast instruction-set simulator for execution profiling, Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems, p.128-137, May 16-20, 1994, Nashville, Tennessee, United States
	6	F. Dahlgren, M. Dubois and P. Stenstr6m, "Fixed and Adaptive Sequential Prefetching in Shared-Memory Multiprocessors", Proc~ 1993 Int. Conf. Parallel Processing, CRC Press, Boca Rat6n, Fla., 1993, pp. 156-.i 63.
	7	Fredrik Dahlgren , Michel Dubois , Per Stenström, Sequential Hardware Prefetching in Shared-Memory Multiprocessors, IEEE Transactions on Parallel and Distributed Systems, v.6 n.7, p.733-746, July 1995 [doi>10.1109/71.395402]
	8	F. Dahlgren , P. Stenstrom, Effectiveness of hardware-based stride and sequential prefetching in shared-memory multiprocessors, Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture, p.68, January 22-25, 1995
	9	K. I. Farkas , N. P. Jouppi , P. Chow, How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors?, Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture, p.78, January 22-25, 1995
	10	John W. C. Fu , Janak H. Patel , Bob L. Janssens, Stride directed prefetching in scalar processors, Proceedings of the 25th annual international symposium on Microarchitecture, p.102-110, December 01-04, 1992, Portland, Oregon, United States
	11	E. Hagersten. "Towards Scalable Cache Only Memory Architectures'', PhD thesis, Swedish Inst. of Comp. Science, Oct. 1992.
	12	P. Ib~fiez and V. Vifials. "Performance Assessment of Contents Management in Multilevel on-chip Caches". In Proc. of the 22nd Euromicro ConF. pp: 431-440, Sept. 1996.
	13	L. Jimeno, P. lb~hez and V. Vifials. "Warm Time-sampling: Fast and Accurate Cycle-level Simulation of Cache Memory''. In Proc. of the 22nd Euromicro Conf. Short Contrib. pp: 39-44, Sept. 1996.
	14	Doug Joseph , Dirk Grunwald, Prefetching using Markov predictors, Proceedings of the 24th annual international symposium on Computer architecture, p.252-263, June 01-04, 1997, Denver, Colorado, United States
	15	Norman P. Jouppi, Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, Proceedings of the 17th annual international symposium on Computer Architecture, p.364-373, May 28-31, 1990, Seattle, Washington, United States
	16	Y. Jégou , O. Temam, Speculative prefetching, Proceedings of the 7th international conference on Supercomputing, p.57-66, July 19-23, 1993, Tokyo, Japan [doi>10.1145/165939.165954]
	17	Luddy Harrison, Examination of a memory access classification scheme for pointer-intensive and numeric programs, Proceedings of the 10th international conference on Supercomputing, p.133-140, May 25-28, 1996, Philadelphia, Pennsylvania, United States [doi>10.1145/237578.237595]
	18	J. M. Mulder, N. T. Quach and M. J. Flynn. "An Area Model For On-Cllip Memories and its Application". IEEE Jour. of Solid State Circuits 26 (2) Feb. 1991, pp. 98-106.
	19	Toshihiro Ozawa , Yasunori Kimura , Shin'ichiro Nishizaki, Cache miss heuristics and preloading techniques for general-purpose programs, Proceedings of the 28th annual international symposium on Microarchitecture, p.243-248, November 29-December 01, 1995, Ann Arbor, Michigan, United States
	20	S. Palacharla , R. E. Kessler, Evaluating stream buffers as a secondary cache replacement, Proceedings of the 21ST annual international symposium on Computer architecture, p.24-33, April 18-21, 1994, Chicago, Illinois, United States
	21	Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982 [doi>10.1145/356887.356892]
	22	Dean M. Tullsen , Susan J. Eggers, Effective cache prefetching on bus-based multiprocessors, ACM Transactions on Computer Systems (TOCS), v.13 n.1, p.57-88, Feb. 1995 [doi>10.1145/200912.201006]
	23	Steven P. VanderWiel , David J. Lilja, When Caches Aren't Enough: Data Prefetching Techniques, Computer, v.30 n.7, p.23-30, July 1997 [doi>10.1109/2.596622]

CITED BY 3

	Chi-Hung Chi , Jun-Li Yuan , Chin-Ming Cheung, Cyclic dependence based data reference prediction, Proceedings of the 13th international conference on Supercomputing, p.127-134, June 20-25, 1999, Rhodes, Greece
	Luis M. Ramos , José Luis Briz , Pablo E. Ibáñez , Victor Viñals, Data prefetching in a cache hierarchy with high bandwidth and capacity, Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures, p.37-44, September 16-20, 2006, Seattle, Washington
	Luis M. Ramos , José Luis Briz , Pablo E. Ibáñez , Victor Viñals, Data prefetching in a cache hierarchy with high bandwidth and capacity, ACM SIGARCH Computer Architecture News, v.35 n.4, September 2007