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Speculative execution model with duplication
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Source International Conference on Supercomputing archive
Proceedings of the 12th international conference on Supercomputing table of contents
Melbourne, Australia
Pages: 321 - 328  
Year of Publication: 1998
ISBN:0-89791-998-X
Authors
Kei Hiraki  Department of Information Science, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-0033 Japan
Junji Tamatsukuri  Department of Information Science, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-0033 Japan
Takashi Matsumoto  Department of Information Science, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-0033 Japan
Sponsors
SIGARCH: ACM Special Interest Group on Computer Architecture
IEEE-CS : Computer Society
Publisher
ACM  New York, NY, USA
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
T. Matsumoto, T. Tanaka, T. Moriyama, and S. Uzuhara: MiSC: A Mechanism for integrated Synchronization and Communication Using Snoop Caches. Proc. of the 1991 Int. Conf. on Parallel Processing, Vol. 1, pp. 161-170, 1991.
 
2
Junji Tamatsukuri , Takashi Matsumoto , Kei Hiraki., "On-Chip Parallel Architecture for Runtime Loop Restructuring" ,Technical Report TR- 04,University of Tokyo, 1997
 
3
Kazuki Yoshizoe, "Java Virtual Machine which speculatively executes loops in parallel", Bachelor Thesis, Department of information science, University of Tokyo, 1997.
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M. Franklin , G. Sohi: ARB:A Hardware Mechanism for Dynamic Reordering of Memory References. Technical report on University of Wisconsin-Madison, 1995
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R. M. Tomasulo: An efficient algorithm for exploring multiple arithmetic units, IBM Journal of Research and Development, Vol. 11, No. 1, pp. 25-33, 1967.
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R. Eickemeyer, S. Vassiliadis: A load-instruction unit for pipelined processors. IBM Journal of Research and Development, Vol. 37, No. 4, pp. 547- 524, 1993.
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S. Damianakis, K. Li, A. Rogers: An Analysis of a Combined Hardware-software Mechanism for Speculative Loads. Technical Report No. 455 on Princeton University, 1994
 
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J. K. F. Lee, A. J. Smith : Branch Prediction Strategies and Branch Target Buffer Design. IEEE Computer, Vol. 17 (January 1984), pp. 6- 22.
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K. Ebcioglu, E. R. Altman: DAISY:Dynamic Compilation for 100% Architectural Compatibility, IBM Reserch Report RC 20538, 1996.

Collaborative Colleagues:
Kei Hiraki: colleagues
Junji Tamatsukuri: colleagues
Takashi Matsumoto: colleagues